Backside gate line slit structure to reduce wafer bow in a three-dimensional memory device comprising bonded devices

A method for forming a three-dimensional memory device, the method comprising the steps of:

• (a) forming a plurality of memory strings through a dielectric stack;
• (b) forming a staircase structure in the dielectric stack to form a memory array device having a frontside and a backside, wherein a cross-sectional diameter of each of the plurality of memory strings increases from the backside of the memory array device towards the frontside of the memory array device;
• (c) forming an etch stop layer on the frontside of the memory array device;
• (d) forming a plurality of interconnections through the etch stop layer to the plurality of memory strings and the staircase structure of the memory array device;
• (e) bonding a peripheral device above the memory array device to the plurality of interconnections;
• and
• (f) forming a backside gate line slit extending through the backside of the memory array device to the etch stop layer, the backside gate line slit comprising a conductive gate line layer and an insulating gate line layer, wherein a cross-sectional diameter of the backside gate line slit decreases from the backside of the memory array device towards the frontside of the memory array device.