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AssigneeSunrise Memory Corporation
InventorsChristopher J. Petti, Eli Harari
Estimating the term…
A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent a semiconductor channel. In some embodiments, the semiconductor channel is formed by an oxide semiconductor material and the ferroelectric storage transistors are junctionless transistors with no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a first conductive layer as a common source line and a second conductive layer as a common bit line, the first and second conductive layers being in electrical contact with the semiconductor channel. The ferroelectric storage transistors in a multiplicity of NOR memory strings are arranged to form semi-autonomous three-dimensional memory arrays (tiles) with each tile individually addressed and controlled by circuitry in the semiconductor substrate underneath each tile in cooperation with a memory controller.
A three dimensional memory structure formed above a planar surface of a semiconductor substrate, the memory structure comprising:
A three dimensional memory structure formed above a planar surface of a semiconductor substrate, the memory structure comprising:
Dependencies are inferred from the claim text.