US 12,615,768 B2Granted

One-time-programmable memory device

AssigneeeMemory Technology Inc.

InventorsLun-Chun Chen, Ping-Lung Ho

Life of this patent

Estimating the term…

Loading patent…

Abstract

A one-time-programmable (OTP) memory device includes a memory array including an N-type memory cell and a P-type memory cell. The N-type memory cell includes first channel layers and second channel layers. The P-type memory cell includes third channel layers and fourth channel layers. The N-type memory cell and the P-type memory cell further include a first word-line gate structure extending in the Y-direction and wrapping around the first channel layers and the third channel layers, and an anti-fuse gate structure extending in the Y-direction and wrapping around the second channel layers and the fourth channel layers. The OTP memory device further includes a wall structure extending in an X-direction and between the N-type memory cell and the P-type memory cell in the Y-direction. The first channel layers, the second channel layers, the third channel layers, and the fourth channel layers attach on the wall structure.

Claims13

Dependent claims

A one-time-programmable (OTP) memory device, comprising:

a memory array, comprising:
an N-type memory cell in a first row, wherein the N-type memory cell comprising:
first channel layers spaced apart from each other in a Z-direction;
a first word-line gate structure extending in a Y-direction and wrapping around the first channel layers;
second channel layers spaced apart from each other in the Z-direction;
and
a anti-fuse gate structure extending in the Y-direction and wrapping around the second channel layers;
a P-type memory cell in a second row adjacent to the first row in the Y-direction, wherein the P-type memory cell comprising:
third channel layers spaced apart from each other in the Z-direction;
the first word-line gate structure wrapping around the third channel layers;
fourth channel layers spaced apart from each other in the Z-direction;
and
the anti-fuse gate structure wrapping around the fourth channel layers;
and
a wall structure extending in an X-direction and between the N-type memory cell and the P-type memory cell in the Y-direction, wherein the first channel layers, the second channel layers, the third channel layers, and the fourth channel layers attach on the wall structure,
wherein when in a programming operation, a turn-on voltage is applied to the first word-line gate structure and a program voltage is applied to the anti-fuse gate structure, such that the N-type memory cell is in a low-impedance storage state and the P-type memory cell is in a high-impedance storage state.

13 more elements

A one-time-programmable (OTP) memory device, comprising:

a memory array, comprising:
an N-type memory cell in a first row, wherein the N-type memory cell comprises:
a first active area extending in an X-direction;
an anti-fuse gate structure extending in a Y-direction and engaging the first active area;
and
a first word-line gate structure and a second word-line gate structure extending in the Y-direction and engaging the first active area;
a P-type memory cell in a second row, wherein the P-type memory cell comprises:
a second active area extending in the X-direction;
the anti-fuse gate structure extending in the Y-direction and engaging the second active area;
and
the first word-line gate structure and the second word-line gate engaging the second active area;
and
a wall structure extending in the X-direction, wherein the first active area and the second active area are disposed on opposite sides of the wall structure,
wherein the first word-line gate structure and the second word-line gate structure are disposed on opposite sides of the anti-fuse gate structure,
wherein the first word-line gate structure and the second word-line gate structure are electrically connected with each other,
wherein in a programming operation, a turn-on voltage is applied to the first word-line gate structure and the second word-line gate structure, a program voltage is applied to the anti-fuse gate structure, such that the N-type memory cell is in a low-impedance storage state and the P-type memory cell is in a high-impedance storage state.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/665,740Filed 16 May 2024 · us provisional application
Priority: 24 May 2023
Published: US 2024/0397710 A128 Nov 2024
Granted: 28 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10B 20/25
Programmable ROM [PROM] devices comprising field-effect components: one-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits
G11C 16/3427
Disturbance prevention or evaluation; Refreshing of disturbed memory data: circuits or methods to prevent or reduce disturbance of the state of a…