Semiconductor device and manufacturing method thereof

A semiconductor device, comprising:

• a substrate including a cell array area, a boundary area, and a peripheral circuit area;
• first active areas defined in the cell array area of the substrate;
• at least one second active area defined in the peripheral circuit area of the substrate;
• bit lines on the cell array area of the substrate, the bit lines extending in a first direction;
• cell pad structures between the bit lines, each of the cell pad structures including a first conductive layer, a first intermediate layer, and a first metal layer sequentially stacked on an upper surface of a corresponding one of the first active areas;
• and
• a peripheral circuit gate electrode on the peripheral circuit area of the substrate, the peripheral circuit gate electrode including a second conductive layer, a second intermediate layer, and a second metal layer sequentially stacked on the at least one second active area, a thickness of each of the cell pad structures being greater than a thickness of the peripheral circuit gate electrode.

A semiconductor device, comprising:

• a substrate including a cell array area, a boundary area, and a peripheral circuit area;
• first active areas defined in the cell array area of the substrate;
• at least one second active area defined in the peripheral circuit area of the substrate;
• bit lines on the cell array area of the substrate, the bit lines extending in a first direction;
• a direct contact between each of the bit lines and a corresponding one of the first active areas, the direct contact electrically connecting each of the bit lines to the corresponding one of the first active areas;
• a direct contact spacer surrounding a sidewall of the direct contact;
• cell pad structures between the bit lines, each of the cell pad structures including a first conductive layer, a first intermediate layer, and a first metal layer sequentially stacked on an upper surface of a corresponding one of the first active areas;
• landing pads on the cell pad structures, respectively;
• and
• a peripheral circuit gate electrode on the peripheral circuit area of the substrate, the peripheral circuit gate electrode including a second conductive layer, a second intermediate layer, and a second metal layer sequentially stacked on the at least one second active area,
• wherein the second metal layer includes a same material as a material included in the first metal layer, and
• wherein the first metal layer has a first height in a vertical direction, the second metal layer has a second height in the vertical direction, the first height is greater than the second height, and a difference between the first height and the second height is equal to or greater than 5 nm.