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US 12,615,762 B2Granted
Three-dimensional dynamic random access memory with stacked semiconductor structures
AssigneeIntel Corporation
InventorsAbhishek Sharma, Tahir Ghani, Anand Murthy, Wilfred Gomes, Sagar Suthram
Life of this patent
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Abstract
Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory. A memory device includes vertically aligned semiconductor structures coupled to independent gate structures, corresponding vertically aligned capacitors each coupled to a corresponding one of the semiconductor structures, and a bit line contact extending vertically across a depth of the semiconductor structures and coupled to each of the semiconductor structures.
Claims22
A memory device, comprising:
- a plurality of vertically aligned semiconductor structures extending laterally;
- a plurality of independent gate structures, each gate structure coupled to a corresponding one of the semiconductor structures;
- a plurality of vertically aligned capacitors, each capacitor coupled to a corresponding one of the semiconductor structures and laterally aligned with a corresponding one of the gate structures and each capacitor comprising a wraparound structure comprising an inner capacitor plate surrounding and in contact with a portion of the corresponding one of the semiconductor structures, a capacitor dielectric surrounding and in contact with the inner capacitor plate, and an outer capacitor plate surrounding and in contact with the capacitor dielectric;
- a bit line contact extending vertically across a depth of the semiconductor structures, the bit line contact coupled to each of the semiconductor structures;
- and
- a shared capacitor contact extending vertically across a depth of the capacitors and in contact with the outer capacitor plates.
3 more elements
A memory device, comprising:
- a plurality of vertically aligned semiconductor structures extending laterally;
- a bit line contact extending vertically across a depth of the semiconductor structures, the bit line contact coupled to each of the semiconductor structures;
- a plurality of first gate structures, each first gate structure coupled to a corresponding one of the semiconductor structures;
- a plurality of second gate structures opposite the bit line from the first gate structures such that the bit line contact is between the first gate structures and the second gate structures, each second gate structure coupled to a corresponding one of the semiconductor structures;
- a plurality of first vertically aligned capacitors, each first capacitor coupled to a corresponding one of the semiconductor structures and laterally aligned with a corresponding one of the first gate structures;
- and
- a plurality of second vertically aligned capacitors opposite the bit line from the first capacitors such that the bit line contact, the first gate structures, and the second gate structures are between the first capacitors and the second capacitors, each second capacitor coupled to a corresponding one of the semiconductor structures and laterally aligned with a corresponding one of the second gate structures.
4 more elements
A memory device, comprising:
- a plurality of vertically aligned semiconductor structures extending laterally;
- a plurality of independent gate structures, each gate structure coupled to a corresponding one of the semiconductor structures;
- a plurality of vertically aligned capacitors, each capacitor coupled to a corresponding one of the semiconductor structures and laterally aligned with a corresponding one of the gate structures;
- and
- a bit line contact extending vertically across a depth of the semiconductor structures, the bit line contact coupled to each of the semiconductor structures and the bit line contact comprising a material epitaxial to each of the semiconductor structures, the material extending vertically across the depth of the semiconductor structures.
2 more elements
Dependencies are inferred from the claim text.