Stacked SRAM with shared wordline connection

An apparatus, comprising:

• a first static random-access memory (SRAM) cell in a first device layer of an integrated circuit (IC) die, the first SRAM cell comprising a first access transistor comprising a first gate electrode;
• a second SRAM cell in a second device layer of the IC die below the first device layer, the second SRAM cell vertically aligned with the first SRAM cell, the second SRAM cell comprising a second access transistor comprising a second gate electrode vertically aligned with the first gate electrode;
• and
• a metallization structure electrically connecting the first gate electrode to the second gate electrode, the metallization structure comprising a substantially vertical portion in contact with a sidewall of the first gate electrode and a sidewall of the second gate electrode.