Vertical interconnect design for improved electrical performance

An electronic assembly comprising:

• a printed circuit board with a first surface and an opposing second surface comprising:
• a plurality of plated through hole vias extending from the first surface to the second surface, the plurality of plated through hole vias comprising:
• a first set of plated through hole vias comprising a first plated through hole via electrically coupled by way of an electrical signal pathway through a pad at either the first surface or the second surface to a second plated through hole via and a first vertical separator being configured between the first and second plated through hole vias, wherein the first vertical separator extends a first depth from the first surface;
• a second set of plated through hole vias comprising a third plated through hole via coupled to a fourth plated through hole via, and a second vertical separator being configured between the third and fourth plated through hole vias, wherein the second vertical separator extends a second depth from the first surface;
• and a connector trace coupling the second plated through hole via to the third plated through hole via, the connector trace being positioned at a third depth from the first surface;
• and
• a plurality of semiconductor devices positioned on the first surface of the printed circuit board.

A method comprising:

• forming a printed circuit board with a first surface and an opposing second surface and at least one embedded connector trace line positioned therebetween;
• forming a plurality of plated through hole vias extending from the first surface to the second surface of the printed circuit board, the plurality of plated through hole vias comprising a first set of plated through hole vias comprising a first plated through hole via and a second plated through hole via, and a second set of plated through holes comprising a third plated through hole via and a fourth plated through hole via, wherein the second plated through hole via is coupled to the third plated through hole via by the embedded connector trace line;
• forming a first metallization layer on the first surface of the printed circuit board and a second metallization on the second surface of the printed circuit board;
• and
• removing a portion of layers of the printed circuit board between the first plated through hole via and the second plated through hole via to form a first vertical separator between the first plated through hole via and the second plated through hole via and a second vertical separator between the third plated through hole via and the fourth plated through hole via.