Inter-chiplet routing of transactions across multi-heterogeneous chiplets using hierarchical addressing

A method comprising:

• receiving, in a die-to-die (D2D) bridge of a first chiplet, a message from a second chiplet;
• accessing a mapping structure using a destination port identifier of message, the destination port identifier comprising a first portion to identify a destination chiplet and a second portion to identify a destination agent on the destination chiplet;
• and
• forwarding the message to another chiplet when the first portion of the destination port identifier identifies the another chiplet;
• and
• forwarding the message to a fabric of the first chiplet to cause the fabric to direct the message to a destination agent of the first chiplet when the first portion of the destination port identifier identifies the first chiplet.

A system comprising:

• a first system on chip (SoC) comprising a multi-heterogenous chiplet package comprising a first chiplet and a second chiplet, the first chiplet comprising:
• a first agent and a second agent, the first and second agents to generate messages, each of the messages having a destination port identifier comprising a first portion to identify a destination chiplet and a second portion to identify a destination agent on the destination chiplet;
• storage to store a first routing table, the first routing table to identify, for each of a plurality of chiplets of the system, a destination chiplet and a routing action;
• a die-to die bridge to couple the first chiplet to the second chiplet, wherein the die-to-die bridge, based on the first routing table, is to send:
• a first message having a first destination port identifier to the second chiplet when the first portion of the first destination port identifier identifies the second chiplet as the destination chiplet;
• and
• a second message having a second destination port identifier to the second chiplet when the first portion of the second destination port identifier identifies a first chiplet of a second SoC as the destination chiplet;
• and
• the second SoC coupled to the first SoC, the second SoC comprising the first chiplet and a third chiplet, wherein the storage of the first chiplet of the second SoC is to store a second routing table, the second routing table different than the first routing table.