Digital calibration of non-linearity in a programmable clock phase circuit

A method for performing digital calibration of non-linearity in a circuit, the method comprising:

• comparing, by a phase detector, a clock signal generated by a programmable clock phase circuit with a reference signal to generate digital phase comparison data indicative of a phase relationship between the clock signal and the reference signal;
• coupling a statistics gathering device that comprises a finite state machine (FSM) to the phase detector to accumulate the digital phase comparison data across multiple delay settings of the programmable clock phase circuit to generate calibration data;
• and
• applying, by a feedback device coupled to the statistics gathering device, digital correction values derived from the calibration data to control a delay and adjust a phase of the clock signal.

A non-transitory computer readable medium comprising stored instructions for performing digital calibration of non-linearity in a programmable clock phase circuit, which when executed by a processor, cause the processor to:

• receive, by a statistics gathering device, digital phase comparison data generated by a phase detector that compares a clock signal from the programmable clock phase circuit with a reference signal;
• accumulate, by the statistics gathering device comprising a finite state machine (FSM), the digital phase comparison data across multiple delay settings of the programmable clock phase circuit to generate calibration data;
• and
• apply, by a feedback device, digital correction values derived from the calibration data to control a programmable delay block and adjust a phase of the clock signal.