Analog-to-digital converter circuit for masking a system clock signal and an image sensor including the same

An image sensor comprising:

• a pixel array including a plurality of pixel circuits disposed at a plurality of rows and a plurality of columns;
• a row decoder configured to sequentially drive the plurality of rows;
• a system clock generator configured to generate a system clock signal;
• an internal clock generator configured to generate a ramp system clock signal and a counter system clock signal based on the system clock signal;
• a ramp generator configured to generate a ramp signal based on the ramp system clock signal;
• a counter clock generator configured to generate a counter clock signal based on the counter system clock signal;
• and
• a first analog-to-digital converter (ADC) connected to pixel circuits, which are located at a first column among the plurality of columns, from among the plurality of pixel circuits through a first column line;
• wherein the first ADC includes:
• a first comparator configured to generate a comparison signal based on a comparison operation of a pixel signal received through the first column line and the ramp signal;
• and
• a first counter configured to generate a digital signal based on the comparison signal and the counter clock signal,
• wherein the internal clock generator is configured to:
• generate the ramp system clock signal by masking the system clock signal for a target clock cycle and generate the counter system clock signal that is identical to the system clock signal;
• or
• generate the ramp system clock signal that is identical to the system clock signal and generate the counter system clock signal by masking the system clock signal for the target clock cycle, and
• wherein the target clock cycle changes each time a row driven by the row decoder from the plurality of rows, changes.

An analog-to-digital converter (ADC) circuit which is connected to first to N-th pixel circuits and a system clock generator, comprising:

• an internal clock generator configured to generate first to N-th clock signals and (N+1)-th to 2N-th clock signals based on a system clock signal received from the system clock generator;
• a ramp generator configured to generate first to N-th ramp signals respectively based on the first to N-th clock signals;
• a counter clock generator configured to generate first to N-th counter clock signals respectively based on the (N+1)-th to 2N-th clock signals;
• and
• a first ADC connected to the first to N-th pixel circuits through a first column line,
• wherein the first ADC includes:
• a first comparator configured to generate first to N-th comparison signals based on comparison operations of first to N-th pixel signals respectively received from the first to N-th pixel circuits and the first to N-th ramp signals;
• and
• a first counter configured to generate first to N-th digital signals based on the first to N-th comparison signals and the first to N-th counter clock signals,
• wherein the internal clock generator is further configured to:
• in synchronization with the sequential driving of the first to N-th pixel circuits, sequentially generate the first to N-th clock signals by masking the system clock signal respectively for first to N-th clock cycles and sequentially generate the (N+1)-th to 2N-th clock signals that are identical to the system clock signal;
• or
• in synchronization with the sequential driving of the first to N-th pixel circuits, sequentially generate the first to N-th clock signals that are identical to the system clock signal and sequentially generate the (N+1)-th to 2N-th clock signals by masking the system clock signal respectively for the first to N-th clock cycles, and
• wherein “N” is an integer greater than or equal to 2.