Inductor based tail current source for current steering DAC
AssigneeCisco Technology, Inc.
InventorsIan Dedic, Darren Walker
Life of this patent
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Abstract
In one embodiment, the disclosure relates to a current steering DAC system. The system may include a current steering digital to analogy converter (DAC) that includes a clock buffer configured to generate a first clock signal having a first frequency and a second clock signal having a second frequency; a tail node; a first clock switch in electrical communication with the tail node; a second clock switch in electrical communication with the tail node; and a current source comprising an inductor having an inductance, the current source in electrical communication with the tail node.
Claims20
A system comprising:
- a current steering digital to analog converter (DAC) comprising,
- a clock buffer configured to generate a first clock signal having a first frequency and a second clock signal having a second frequency;
- a tail node;
- a first clock switch in electrical communication with the tail node;
- a second clock switch in electrical communication with the tail node;
- a current source comprising an inductor having an inductance L, the current source in electrical communication with the tail node;
- and
- one or more data switches in electrical communication with the first clock switch and second clock switch and configured to receive digital communication data that is converted to analog signals, wherein the first clock switch and second clock switch are positioned between the one or more data switches and the inductor.
A method comprising:
- providing a current steering digital to analog converter (DAC) comprising a clock buffer;
- providing a current source comprising an inductor having an inductance L, the current source in electrical communication with a tail node;
- generating, using the clock buffer, a first clock signal having a first frequency;
- generating, using the clock buffer, a second clock signal having a second frequency, wherein the first frequency is fCLK and the second frequency is fCLK;
- resonating the inductor at a frequency of about 2fCLK;
- and
- receiving, at one or more data switches in electrical communication with a first clock switch and a second clock switch, digital communication data that is converted to analog signals, wherein the first clock switch and second clock switch are positioned between the one or more data switches and the inductor.
A system comprising:
- a current steering digital to analog converter (DAC) comprising,
- a clock buffer configured to generate a first clock signal having a first frequency and a second clock signal having a second frequency;
- a tail node;
- a first clock switch in electrical communication with the tail node;
- a second clock switch in electrical communication with the tail node;
- and
- a current source comprising an inductor having an inductance L, the current source in electrical communication with the tail node, wherein inductance at the tail node is tuned until 2fCLK=1/2π√{square root over (LCparasite)}, wherein Cparasitic is the parasitic capacitance of the current source.
Dependencies are inferred from the claim text.