Calibration for sampling methods and systems
AssigneeAlphacore, Inc.
InventorsSachin Namboodiri, Phaneendra Bikkina
Life of this patent
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Abstract
A calibration unit for a sampling system, a sampling system and a method for sampling. The calibration unit for a sampling system includes an oscillator having a number of cycles, a digital counter configured to capture a count value that is representative of a time duration to complete the number of cycles, a digital integrator configured to accumulate a difference between a predetermined count value and the captured count value, and a digital to analog converter (DAC) configured to translate an output from the digital integrator to an analog input for delay cells in the sampling system.
Claims20
A sampling system, the sampling system comprising:
- a plurality of sampling cells;
- and
- a plurality of calibration units connected to the sampling cells and configured to correct a plurality of timing mismatches in the sampling cells, wherein the sampling cells are distributed into a plurality of sampling channels, and wherein the sampling cells in the sampling channels are driven by a plurality of sampling clock pulses with a plurality of respective phase offsets,
- wherein one of the calibration units comprises:
- an oscillator having a number of cycles;
- a digital counter configured to capture a count value that is representative of a time duration to complete the number of cycles;
- a digital integrator configured to accumulate a difference between a predetermined count value and the captured count value;
- and
- a digital to analog converter (DAC) configured to translate an output from the digital integrator into an analog input for a plurality of delay cells in one of the sampling cells of the sampling system for correcting one of the timing mismatches in the sampling system.
A sampling system, the sampling system comprising:
- a plurality of sampling cells;
- and
- a plurality of calibration units connected to the sampling cells and configured to correct a plurality of timing mismatches in the sampling cells, wherein the sampling cells are distributed into a plurality of sampling channels, wherein the sampling cells in the sampling channels are driven by a plurality of sampling clock pulses with a plurality of respective phase offsets,
- wherein each of the sampling cells comprises a sampling switch, a capacitor, a buffer, a readout switch, and a delay cell, wherein the sampling switch and the capacitor are configured to capture and store analog data, and wherein the readout switch and the buffer are configured to read the stored analog data.
A sampling system, the sampling system comprising:
- a plurality of sampling cells;
- and
- a plurality of calibration units connected to the sampling cells and configured to correct a plurality of timing mismatches in the sampling cells, wherein the sampling cells are distributed into a plurality of sampling channels, and wherein the sampling cells in the sampling channels are driven by a plurality of sampling clock pulses with a plurality of respective phase offsets,
- wherein the sampling system further comprises a clock circuit configured to generate the sampling clock pulses with the respective phase offsets, wherein the clock circuit comprises an interpolator configured to generate the respective phase offsets for the sampling clock pulses that are tunable to adjust a plurality of timing delays between the sampling channels.
Dependencies are inferred from the claim text.