Semiconductor device

A semiconductor device comprising:

• a multiphase clock generator configured to generate a first clock signal and a second clock signal having a phase inverted from the first clock signal using a data clock signal, to adjust the phase of the second clock signal based on a first control code, and to output a multiphase clock including the first clock signal and the second clock signal;
• a first serializer configured to output a first serial signal by serializing a first data sequence using the multiphase clock;
• a second serializer configured to output a second serial signal by serializing a second data sequence using the multiphase clock;
• a phase error detector connected to the first serializer and the second serializer and configured to output a first comparison result by comparing a first rising period of the first serial signal and a second rising period of the second serial signal;
• and
• a control logic configured to:
• control the first serializer to generate the first serial signal having the first rising period between a first rising edge of the first clock signal and a second rising edge of the second clock signal by inputting the first data sequence to the first serializer, control the second serializer to generate the second serial signal having the second rising period between the second rising edge of the second clock signal and the first rising edge of the first clock signal by inputting the second data sequence to the second serializer,
• obtain the first comparison result from the phase error detector, and
• correct the phase of the second clock signal by determining a value of the first control code based on the first comparison result.

A semiconductor device, comprising:

• a multiphase clock generator configured to:
• generate a plurality of clock signals by dividing a data clock signal,
• adjust a phase of each of the plurality of clock signals based on a control code set to generate a plurality of phase-adjusted clock signals, and
• output the plurality of phase-adjusted clock signals as a multiphase clock;
• a phase error detector configured to:
• generate a plurality of pulse clock signals from the plurality of phase-adjusted clock signals, wherein each of the plurality of pulse clock signals has a rising period between rising edges of corresponding two adjacent phase-adjusted clock signals among the plurality of phase-adjusted clock signals, and wherein the corresponding two adjacent phase-adjusted clock signals are selected from the plurality of phase-adjusted clock signals based on a select signal, and
• output a plurality of comparison results, wherein each of the plurality of comparison results is obtained by comparing a direct current level corresponding to a length of a rising period of a corresponding one of the plurality of pulse clock signals and a reference level corresponding to an input digital code value;
• a register configured to store the control code set, the select signal and the plurality of comparison results;
• and
• a control logic connected to access to the register, and configured to:
• repeatedly perform an operation of determining a corresponding digital code value corresponding to the direct current level by performing a search for candidate input digital code values on the plurality of pulse clock signals to generate a plurality of corresponding digital code values of the plurality of pulse clock signals,
• determine a reference value based on the plurality of corresponding digital code values of the plurality of pulse clock signals,
• determine the control code set in which each of the plurality of corresponding digital code values of the plurality of pulse clock signals is equalized to the reference value, and
• correct a phase of the multiphase clock by inputting the determined control code set to the register.