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US 12,615,049 B2Granted
Field Programmable Gate Array system
AssigneeRebellions Inc.
InventorsKyeongryeol Bong, Juyeong Yoon
Life of this patent
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Abstract
A Field Programmable Gate Array (FPGA) system includes a main FPGA and one or more sub-FPGAs connected to the main FPGA. The main FPGA is configured to detect a positive edge of a pulse included in a user clock using a sampling clock of the main FPGA, generate a flag using the detected positive edge, generate a clock packet indicating the generated flag, and provide the generated clock packet to any one of the one or more sub-FPGAs.
Claims20
A Field Programmable Gate Array (FPGA) configured to:
- detect a positive edge of a pulse included in a user clock using a sampling clock of the FPGA;
- generate a flag using the detected positive edge;
- generate a clock packet indicating the generated flag;
- and
- provide the generated clock packet to any one of one or more sub-FPGAs connected to the FPGA.
2 more elements
A Field Programmable Gate Array (FPGA) configured to:
- receive, from a main-FPGA connected to the FPGA, a clock packet indicating a flag,
- wherein the flag is generated, using a positive edge of a pulse included in a user clock, and
- the positive edge is detected, using a sampling clock of the main-FPGA.
Dependencies are inferred from the claim text.