Duty cycle correction circuit

A duty cycle correction circuit, comprising:

• a signal input terminal and a signal output terminal;
• a signal adjustment circuit electrically connected to the signal input terminal and the signal output terminal, respectively;
• wherein the signal adjustment circuit is configured to receive a first clock signal input from the signal input terminal, convert the first clock signal into a second clock signal and output the second clock signal from the signal output terminal;
• a duty cycle detection circuit electrically connected to the signal adjustment circuit;
• wherein the duty cycle detection circuit is configured to detect a duty cycle of the second clock signal and generate a feedback result;
• and
• a digital control delay circuit electrically connected to the duty cycle detection circuit, the signal adjustment circuit and the signal input terminal, respectively;
• wherein digital control delay circuit is configured to, according to the feedback result, perform a corresponding delay operation on the first clock signal to adjust the duty cycle of the second clock signal.