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US 12,615,041 B2Granted
Duty cycle corrector, semiconductor device including the same, and operating method of duty cycle corrector
AssigneeSamsung Electronics Co., Ltd.
InventorsWooseuk Oh, Donguk Park, Kihwan Seong, Byoungjoo Yoo
Life of this patent
Estimating the term…
Abstract
A duty cycle corrector (DCC) includes a first duty cycle correction circuit, a second duty cycle correction circuit, and overshoot prevention circuit connected between the first duty cycle correction circuit and the second duty cycle correction circuit. Each of the duty cycle correction circuits include a capacitor, two inverters, a resister, and two switches.
Claims20
A duty cycle corrector (DCC) comprising:
- a first capacitor connected between a terminal receiving a first input clock signal and a first node;
- a first inverter connected between the first node and a second node;
- a second inverter connected between the second node and a terminal outputting a first output clock signal;
- a first resistor connected between the first node and the second node;
- a first switch connected between the first node and a terminal receiving a ground voltage;
- a second switch connected between the second node and the first resistor;
- a second capacitor connected between a terminal receiving a second input clock signal and a third node, where the first input clock signal and the second input clock signal form a differential signal pair;
- a third inverter connected between the third node and a fourth node;
- a fourth inverter connected between the fourth node and a terminal outputting a second output clock signal;
- a second resistor connected between the third node and the fourth node;
- a third switch connected between the third node and a terminal receiving a supply voltage;
- a fourth switch connected between the fourth node and the second resistor;
- and
- an overshoot prevention circuit connected between the first node and the third node.
11 more elements
A duty cycle corrector (DCC) comprising:
- a first duty cycle correction circuit configured to receive a first input clock signal and comprising a first alternating current (AC) coupling capacitor and a first inverter connected to a first feedback resistor;
- a second duty cycle correction circuit configured to receive a second input clock signal and comprising a second AC coupling capacitor and a third inverter connected to a second feedback resistor;
- and
- an overshoot prevention circuit connected between a first node connecting the first AC coupling capacitor to the first inverter and a third node connecting the second AC coupling capacitor to the third inverter.
1 more element
A semiconductor device comprising:
- a clock generator including a duty cycle corrector (DCC),
- wherein the DCC comprises:
- a first duty cycle correction circuit configured to receive a first input clock signal and comprising a first alternating current (AC) coupling capacitor and a first inverter connected to a first feedback resistor;
- a second duty cycle correction circuit configured to receive a second input clock signal and comprising a second AC coupling capacitor and a third inverter connected to a second feedback resistor;
- and
- an overshoot prevention circuit connected between a first node connecting the first AC coupling capacitor to the first inverter and a third node connecting the second AC coupling capacitor to the third inverter.
3 more elements
Dependencies are inferred from the claim text.