US 12,615,037 B2 · Multi-master control circuit

Abstract

A multi-master control circuit includes signal switch, D-type flip-flop, and multiplexer. The signal switch outputs switching signals based on a first control signal generated by a first processor or a second control signal generated by a second processor. The D-type flip-flop includes clock input, signal input, signal output, and inverted signal output. The clock input is coupled to the signal switch to receive the switching signals, and the inverted signal output is coupled to the signal input. Upon triggering by the switching signals, the signal output of the D-type flip-flop generates a selection signal. The multiplexer receives a first access signal generated by the first processor and a second access signal generated by the second processor. The multiplexer is coupled to the signal output of the D-type flip-flop to receive the selection signal and output either the first access signal or the second access signal based on the selection signal.

Claims20

Dependent claims

A multi-master control circuit, coupled to a first processor and a second processor, wherein the multi-master control circuit comprises:

a signal switch, receiving a first control signal generated by the first processor and a second control signal generated by the second processor, and outputting switching signals based on the first control signal and the second control signal;
a D-type flip-flop, comprising clock input, signal input, signal output, and inverted signal output, wherein the clock input is coupled to the signal switch to receive the switching signals, the inverted signal output is coupled to the signal input, and upon triggering by the switching signals, the signal output of the D-type flip-flop generates a selection signal;
and
a multiplexer, receiving a first access signal generated by the first processor and a second access signal generated by the second processor, wherein the multiplexer is coupled to the signal output of the D-type flip-flop to receive the selection signal and output either the first access signal or the second access signal based on the selection signal.

1 more element

A multi-master control circuit, comprising:

a first processor, receiving a feedback signal, and determining, based on the feedback signal, whether to generate a first control signal;
a second processor, receiving the feedback signal, and determining, based on the feedback signal, whether to generate a second control signal;
a signal switch, receiving the first control signal and the second control signal, and outputting switching signals based on the first control signal and the second control signal;
a D-type flip-flop, comprising clock input, signal input, signal output, and inverted signal output, wherein the clock input is coupled to the signal switch to receive the switching signals, the inverted signal output is coupled to the signal input, the first processor, and the second processor, and upon triggering by the switching signals, the signal output of the D-type flip-flop generates a selection signal, and the inverted signal output generates the feedback signal;
and
a multiplexer, receiving a first access signal generated by the first processor and a second access signal generated by the second processor, wherein the multiplexer is coupled to the signal output of the D-type flip-flop to receive the selection signal and output either the first access signal or the second access signal based on the selection signal.

3 more elements

Dependencies are inferred from the claim text.

Multi-master control circuit

Life of this patent

Multi-master control circuit

Life of this patent

Abstract

Claims20