Fast clock switching deglitch circuit

An apparatus comprising:

• a selector circuit to switch a source for an internal clock signal from a first clock signal to a second clock signal according to an internal switch signal, the first and second clock signals being asynchronous;
• wherein the internal clock signal has a narrower high portion than a high portion of the second clock signal during a first period of the internal clock signal after the switch from the first clock signal to the second clock signal, the narrower high portion indicative of a glitch;
• masking logic to generate a masking signal that is asserted during the glitch;
• and
• a logic circuit to logically combine the internal clock signal and the masking signal to generate an output clock signal.

An apparatus comprising:

• a selector circuit to switch a source for an internal clock signal from a first clock signal to a second clock signal responsive to a change in value of a delayed select signal, the first and second clock signals being asynchronous;
• wherein the internal clock signal has a narrower high portion during a first period of the internal clock signal after the switch from the first clock signal to the second clock signal, the narrower high portion being narrower than a next high portion of the internal clock signal after the narrower high portion;
• masking logic to generate a masking signal that is asserted during the narrower high portion;
• a logic circuit to logically combine the internal clock signal and the masking signal to generate an output clock signal;
• and
• wherein the masking signal is enabled responsive to a last falling edge of the internal clock signal before the switch and the masking signal is disabled responsive to a first falling edge of the internal clock signal after the switch.