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US 12,615,021 B1Granted
High speed RF switch method employing differential current cancellation
AssigneeNational Technology & Engineering Solutions of Sandia, LLC
InventorTravis Forbes
Life of this patent
Estimating the term…
Abstract
A radio frequency (RF) switch employing differential signal cancellation is disclosed. The differential RF switch enables high isolation and extremely small size by employing cascode current steering within a differential switching amplifier. Unlike series RF switches, isolation with the differential RF switch is limited by device mismatch, not switch parasitic capacitance, enabling high frequency operation. Since the differential RF switch can be placed within the already present cascode devices, there is no additional insertion loss from the switch.
Claims14
A differential switching amplifier comprising:
- positive and negative inverting input transistors adapted to receive corresponding positive and negative input voltages and to convert the corresponding positive and negative input voltages into respective negative and positive input currents;
- positive and negative output terminals adapted to output corresponding positive and negative output currents;
- a pair of always on cascode transistors, each of the pair of always on cascode transistors having a width of W/2, a first of the pair of always on cascode transistors adapted to couple half of the negative input current to the negative output terminal, a second of the pair of always on cascode transistors adapted to couple half of the positive input current to the positive output terminal;
- a pair of enabled cascode transistors adapted to receive an enable gate signal (EN), each of the pair of enabled cascode transistors having a width of W/2, a first of the pair of enabled cascode transistors adapted to couple half of the negative input current to the negative output terminal when EN is high and to couple no current to the negative output terminal when EN is low, a second of the pair of enabled cascode transistors adapted to couple half of the positive input current to the positive output terminal when EN is high and to couple no current to the positive output terminal when EN is low;
- a pair of bar enabled cascode transistors adapted to receive a bar enable gate signal (ENB), wherein ENB is a logical opposite of EN, each of the pair of bar enabled cascode transistors having a width of W/2, a first of the pair of bar enabled cascode transistors adapted to couple half of the negative input current to the positive output terminal when ENB is high and to couple no current to the positive output terminal when ENB is low, a second of the pair of bar enabled cascode transistors adapted to couple half of the positive input current to the negative output terminal when ENB is high and to couple no current to the negative output terminal when ENB is low;
- and
- a pair of always off cascode transistors, each of the pair of always off cascode transistors having a width of W/2, a first of the pair of always off cascode transistors coupled between the positive inverting input transistor and the negative output terminal, a second of the pair of always off cascode transistors coupled between the negative inverting input transistor and the positive output terminal.
4 more elements
An RF system comprising:
- an antenna adapted to transmit and receive RF signals;
- a baseband and processing element adapted to process baseband signals;
- and
- receive and transmit differential switching amplifiers, the receive differential switching amplifier adapted to receive an RF signal from the antenna and to output an amplified/switched signal to the baseband and processing element, the transmit differential switching amplifier adapted to receive an RF signal from the baseband and processing element and to output an amplified/switched signal to the antenna, each of the receive and transmit differential switching amplifiers including:
- positive and negative inverting input transistors adapted to receive corresponding positive and negative input voltages corresponding to an RF signal and to convert the corresponding positive and negative input voltages into respective negative and positive input currents;
- positive and negative output terminals adapted to output corresponding positive and negative output currents;
- a pair of always on cascode transistors, each of the pair of always on cascode transistors having a width of W/2, a first of the pair of always on cascode transistors adapted to couple half of the negative input current to the negative output terminal, a second of the pair of always on cascode transistors adapted to couple half of the positive input current to the positive output terminal;
- a pair of enabled cascode transistors adapted to receive an enable gate signal (EN), each of the pair of enabled cascode transistors having a width of W/2, a first of the pair of enabled cascode transistors adapted to couple half of the negative input current to the negative output terminal when EN is high and to couple no current to the negative output terminal when EN is low, a second of the pair of enabled cascode transistors adapted to couple half of the positive input current to the positive output terminal when EN is high and to couple no current to the positive output terminal when EN is low;
- and
- a pair of bar enabled cascode transistors adapted to receive a bar enable gate signal (ENB), wherein ENB is a logical opposite of EN, each of the pair of bar enabled cascode transistors having a width of W/2, a first of the pair of bar enabled cascode transistors adapted to couple half of the negative input current to the positive output terminal when ENB is high and to couple no current to the positive output terminal when ENB is low, a second of the pair of bar enabled cascode transistors adapted to couple half of the positive input current to the negative output terminal when ENB is high and to couple no current to the negative output terminal when ENB is low;
- wherein each of the receive and transmit differential switching amplifiers further includes a pair of always off cascode transistors, each of the pair of always off cascode transistors having a width of W/2, a first of the pair of always off cascode transistors coupled between the positive inverting input transistor and the negative output terminal, a second of the pair of always off cascode transistors coupled between the negative inverting input transistor and the positive output terminal.
8 more elements
Dependencies are inferred from the claim text.