Semiconductor device and memory device including sampling circuit
AssigneeSK hynix Inc.
InventorsJun Seok Noh, Woongrae Kim
Life of this patent
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Abstract
A semiconductor device includes a random number generation circuit configured to generate a plurality of random signals according to a sampling signal; an active counter configured to count a number of inputs of an active command during a sampling period defined by the sampling signal to generate an active count signal; a replacement control circuit configured to compare the active count signal with each of the plurality of random signals to generate a replacement control signal; and a sampling latch configured to replace a sampling address with an input address according to the replacement control signal, and output the sampling address according to the sampling signal.
Claims20
A semiconductor device comprising:
- a random number generation circuit configured to generate a plurality of random signals according to a sampling signal;
- an active counter configured to count a number of inputs of an active command during a sampling period defined by the sampling signal to generate an active count signal;
- a replacement control circuit configured to compare the active count signal with each of the plurality of random signals to generate a replacement control signal;
- and
- a sampling latch configured to replace a sampling address with an input address according to the replacement control signal, and output the sampling address according to the sampling signal.
A memory device comprising:
- a plurality of rows;
- a sampling control circuit configured to count a number of inputs of an active command during a target refresh period defined by a target refresh signal to generate an active count signal, and compare the active count signal with each of a plurality of random signals to generate a replacement control signal;
- a sampling latch configured to replace a sampling address with an active address according to the replacement control signal, and output the sampling address as a target address according to the target refresh signal;
- and
- a row control circuit configured to refresh at least one row corresponding to the target address, among the plurality of rows, according to the target refresh signal.
Dependencies are inferred from the claim text.