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US 12,614,605 B2Granted
Sequential access to linked memory dice for bus training
AssigneeMicron Technology, Inc.
InventorsSmruti Subhash Jhaveri, Hyunyoo Lee
Life of this patent
Estimating the term…
Abstract
During a command bus training (CBT), interconnected memory dice are accessed in a sequence determined (e.g., predetermined) by a bit sequence generator and via a shared data link for retrieving a respective set of feedback data of the CBT from each memory dice. This eliminates a need to individually train and/or control interconnected memory dice for the CBT; thereby, providing a flexible and scalable architecture that can accommodate a range of memory densities (e.g., a number of memory dice that are interconnected) and making it a valuable solution for high-performance memory applications.
Claims19
A method, comprising:
- determining a sequence at which a set of memory dice that are linked together are accessed, wherein each memory die of the set of memory dice comprises a respective command/address (CA) signal receiver that is directly coupled to a CA bus, the set of memory dice further including:
- a primary memory die coupled to an external data bus;
- and
- a number of secondary memory dice coupled to the primary memory die respectively via a number of wire links;
- and
- accessing the set of memory dice one at a time in the determined sequence by:
- receiving, at a respective memory die of the set of memory dice, first data corresponding to a test data pattern at the CA signal receiver directly from the CA bus;
- and
- sending the first data from respective memory dice of the set of memory dice in the determined sequence on the external data bus.
6 more elements
An apparatus, comprising:
- a set of memory dice comprising:
- a primary memory die comprising a bit sequence generator and coupled to a substrate via a first external data bus and a command/address (CA) bus;
- and
- a number of secondary memory dice each individually comprising:
- a respective CA signal receiver that is directly coupled to the CA bus;
- and
- a respective bit sequence generator and coupled to the primary memory die via a number of wire links in a cascaded manner;
- and
- wherein one or more of the bit sequence generator of the primary memory die and the respective bit sequence generators of the number of secondary memory dice are configured to determine a sequence in which memory dice of the first set are accessed;
- wherein the primary memory die is configured to send data from the primary memory die or data received from one of the number of secondary memory dice on the first external data bus;
- and
- wherein each secondary memory die of the number of secondary memory dice is configured to send data from the respective secondary memory die or a different secondary memory die to the primary memory die via one or more wire links of the number of wire links to cause the data to be sent from the primary memory die on the first external data bus.
9 more elements
An apparatus, comprising:
- a first set of memory dice coupled to a substrate via a command/address (CA) bus and a first external data bus, wherein the first set of memory dice comprise:
- a first primary memory die comprising a CA signal receiver that is directly coupled to the CA bus and to the substrate via the CA bus;
- and
- a number of first secondary memory dice, each of the number of first secondary memory dice comprising a respective CA signal receiver that is directly coupled to the CA bus, wherein the number of first secondary memory dice further coupled to the first primary memory die via respective first wire links in a cascaded manner;
- and
- a second set of memory dice comprising:
- a second primary memory die comprising a CA signal receiver that is directly coupled to the CA bus and to the substrate via the CA bus;
- and
- a number of second secondary memory dice coupled to, each of the number of second secondary memory dice comprising a respective CA signal receiver that is directly coupled to the CA bus, wherein the number of second secondary memory dice further coupled to the second primary memory die via respective second wire links in a cascaded manner;
- and
- wherein one or more memory dice of the first set of memory dice comprises a bit sequence generator;
- wherein one or more memory dice of the second set of memory dice comprises a bit sequence generator;
- and
- wherein the bit sequence generators of the one or more memory dice of the first set of memory dice or the bit sequence generators of the one or more memory dice of the second set of memory dice, or both, are configured to determine a sequence in which respective memory dice of the first set of memory dice or the second set of memory dice, or both, are accessed.
11 more elements
Dependencies are inferred from the claim text.