US 12,614,603 B2Granted

Area saving high coverage fast diagnosis memory scan design

AssigneeSTMicroelectronics International N.V.

InventorsPraveen Kumar Verma, Christophe Lecocq, Yagnesh Dineshbhai Vaderiya, Anuj Dhillon, Cedric Escallier, Harsh Rawat, Kedar Janardan Dhori

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Abstract

A memory system disclosed herein features left and/or right memory banks, with left and/or right input/output (IO) blocks aligned with the memory banks for managing data input and output. A control section, situated between the left and right input/output blocks, oversees memory operations, receives control signals, and performs stuck-at testing. The control section includes fault detection logic designed to output a first logic value (e.g., logic low) if logic values at each of its external inputs are identical, but output a second logic value (e.g., logic high) if not. The fault detection logic is capable of detecting stuck-at faults in the external inputs by performing both stuck-at-0 and stuck-at-1 testing. If only stuck-at-0 or stuck-at-1 faults are detected, the fault detection logic can pinpoint those faults by iteratively changing input values at each of its external inputs and observing the output of the fault detection logic.

Claims23

Dependent claims

A memory system, comprising:

a left memory bank;
a left input/output block aligned with said left memory bank for handling data input and output for the left memory bank;
a right memory bank;
a right input/output block aligned with said right memory bank for handling data input and output for the right memory bank;
a row decoder situated between the left memory bank and the right memory bank and configured to select a specific row within the left memory bank and/or the right memory bank based on an address input;
a control section situated between said left and right input/output blocks for managing memory operations, receiving control signals including address signals, functional commands, and debug commands and data, and performing stuck-at testing;
and
a fault detection logic within said control section configured to output a first logic value if all of its external inputs are identical and output a second logic value if not, the fault detection logic further configured to detect and locate stuck-at faults in the external inputs to the fault detection logic by:
performing stuck-at-0 testing by receiving each of the external inputs as the second logic value and observing whether the output of the fault detection logic is the second logic value;
and
performing stuck-at-1 testing by receiving each of the external inputs as the first logic value and observing whether the output of the fault detection logic is the second logic value.

8 more elements

A method for testing a memory device including a first memory core, a first IO block associated with the first memory core, a row decoder, and a control block, the method comprising:

performing stuck-at-0 testing using a fault detection circuit within the control block by causing each input value to the fault detection circuit, including address inputs provided to the row decoder, to be set to a second logic value so that the fault detection circuit outputs a first logic value to indicate a lack of a stuck-at-0 fault but otherwise outputs the second logic value to indicate a stuck-at-0 fault;
performing stuck-at-1 testing using the fault detection circuit by causing each input value to the fault detection circuit, including the address inputs provided to the row decoder, to be set to the first logic value so that the fault detection circuit outputs the first logic value to indicate a lack of a stuck-at-1 fault but otherwise outputs the second logic value to indicate a stuck-at-1 fault;
if stuck-at-1 faults are not indicated, pinpointing indicated stuck-at-0 faults by iteratively changing the input values, including the address inputs provided to the row decoder, and observing the output of the fault detection circuit;
and
if stuck-at-0 faults are not indicated, pinpointing indicated stuck-at-1 faults by iteratively changing the input values, including the address inputs provided to the row decoder, and observing the output of the fault detection circuit.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/635,569Filed 15 Apr 2024 · us provisional application
Priority: 26 Apr 2023
Published: US 2024/0363187 A131 Oct 2024
Granted: 28 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 29/46
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: test trigger logic
G11C 29/022
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in I/O circuitry
G11C 29/10
Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing: test algorithms, e.g. memory scan [MScan]…
G11C 29/32
Accessing single arrays: serial access; Scan testing