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US 12,614,601 B2Granted
Memory apparatus and semiconductor system including the same
AssigneeSK hynix Inc.
InventorsHeeeun Choi, Yeong Han Jeong
Life of this patent
Estimating the term…
Abstract
A memory apparatus includes an address decoding circuit configured to output a test redundancy address based on an address that is transmitted from a memory controller; and a redundancy address check circuit configured to determine whether the test redundancy address is replacing a failed address, in order to perform an ECC test operation by using the test redundancy address.
Claims15
A memory apparatus comprising:
- a plurality of redundancy regions;
- and
- a redundancy address check circuit configured to determine whether a test redundancy address is usable for an error correcting code (ECC) test operation by comparing the test redundancy address with a reference address, among a plurality of redundancy addresses, corresponding to the redundancy regions.
A semiconductor system comprising:
- a memory apparatus with an ECC circuit, the memory apparatus configured to perform an ECC test operation for the ECC circuit;
- and
- a memory controller configured to transmit an address to the memory apparatus for the ECC test operation,
- wherein the memory apparatus determines a test redundancy address that corresponds to the address, compares the test redundancy address with a reference address among a plurality of redundancy addresses, and outputs a warning signal to the memory controller when it is determined that the test redundancy address is unusable for the ECC test operation based on a comparison result.
1 more element
An operating method of a memory apparatus, the operating method comprising:
- comparing a test redundancy address with a reference address among a plurality of redundancy addresses;
- storing data including an error in a redundancy region corresponding to the test redundancy address according to a comparison result;
- reading stored data from the redundancy region;
- performing an error correction operation on read data;
- and
- outputting a result of the error correction operation.
3 more elements
Dependencies are inferred from the claim text.