Multi-level cell data encoding
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWin-San Khwa, Jui-Jen Wu, Jen-Chieh Liu, Meng-Fan Chang
Life of this patent
Estimating the term…
Abstract
A system includes a memory cell array including multi-level cells, an input data scramble circuit configured to receive input data and match lower error tolerant bits with higher error tolerant bits to provide matched bit sets, wherein each of the matched bit sets includes at least one lower error tolerant bit and at least one higher error tolerant bit, and a write driver configured to receive the matched bit sets and store each of the matched bit sets into one memory cell of the multi-level cells.
Claims20
A convolutional neural network system, comprising:
- a memory cell array including multi-level cells configured to store convolutional neural network weights;
- an input data scramble circuit configured to receive convolutional neural network weights that each have a most significant bit that is a highest order bit in the convolutional neural network weight and a least significant bit that is a lowest order bit in the convolutional neural network weight and the input data scramble circuit is configured to match higher order bits that are lower error tolerant bits that if inadvertently changed have a larger negative impact on inferences made by the convolutional neural network system with lower order bits that are higher error tolerant bits that if inadvertently changed have a smaller negative impact on inferences made by the convolutional neural network system to provide matched bit sets;
- and
- a write driver configured to receive the matched bit sets and store each of the matched bit sets into a memory cell of the multi-level cells.
A convolutional neural network system, comprising:
- a memory cell array including multi-level cells configured to store convolutional neural network weights;
- an input data scramble circuit configured to receive convolutional neural network weights that each have a most significant bit that is a highest order bit in the convolutional neural network weight and a least significant bit that is a lowest order bit in the convolutional neural network weight and the input data scramble circuit is configured to pair the most significant bit minus n and the least significant bit plus n, where n is a non-negative integer, of the convolutional neural network weights to provide pairs of bits;
- and
- a write driver configured to receive the pairs of bits and store each pair of bits of the pairs of bits in a multi-level cell of the multi-level cells.
A method, comprising:
- obtaining input data that includes convolutional neural network weights that each have a most significant bit that is a highest order bit in the convolutional neural network weight and a least significant bit that is a lowest order bit in the convolutional neural network weight;
- matching, by an input data scramble circuit, higher order bits of the convolutional neural network weights that are lower error tolerant bits that if inadvertently changed have a larger negative impact on inferences made by the convolutional neural network system with lower order bits of the convolutional neural network weights that are higher error tolerant bits that if inadvertently changed have a smaller negative impact on inferences made by the convolutional neural network system to provide matched bit sets;
- outputting the matched bit sets to a write driver;
- and
- storing, by the write driver, the matched bit sets in multi-level cells of a memory cell array.
Dependencies are inferred from the claim text.