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US 12,614,591 B2Granted
Apparatus and methods for negative threshold voltages for nonvolatile memory devices
AssigneeSanDisk Technologies LLC
InventorsWei Cao, Xiang Yang, Jiahui Yuan, Deepanshu Dutta
Life of this patent
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Abstract
The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells are programmed according to a one bit per memory cell (SLC) programming scheme that includes an erased data state and a programmed data state. The memory cells in both the erased data state and in the programmed data state have threshold voltages Vt that are less than 0 V.
Claims20
A method of operating a memory device, comprising the steps of:
- preparing a memory device that includes a memory block with an array of memory cells that are arranged in a plurality of word lines;
- programming the memory cells of a selected word line of the plurality of word lines according to a one bit per memory cell (SLC) storage scheme that includes an erased data state and a programmed data state;
- and
- wherein both the memory cells in the erased data state and the memory cells in the programmed data state have threshold voltages that are less than 0 V.
1 more element
A memory device, comprising:
- a memory block with an array of memory cells that are arranged in a plurality of word lines;
- and
- the memory cells being programmed according to a one bit per memory cell (SLC) programming scheme that includes an erased data state and a programmed data state, and wherein the memory cells in both the erased data state and in the programmed data state have threshold voltages that are less than 0 V.
A computing system, comprising:
- a processor unit;
- a plurality of high bandwidth flash (HBF) packages in electrical communication with the processor unit;
- at least one of the HBF packages including a memory block with an array of memory cells that are arranged in a plurality of word lines, the memory cells being programmed according to a one bit per memory cell (SLC) programming scheme that includes an erased data state and a programmed data state, and wherein the memory cells in both the erased data state and in the programmed data state have threshold voltages that are less than 0 V.
Dependencies are inferred from the claim text.