Variation tolerant reconfigurable replica bitline circuits
AssigneeIntel Corporation
InventorsNaveen Kumar, Gururaj Shamanna, Jagadeesh Chandra Salaka, Purna Chandra Nayak
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Abstract
An apparatus, system, and method for improved replica bit line (RBL) operation are provided. An memory control circuit can include an RBL including a plurality of replica bit cells (RBCs) electrically coupled in series, a timer and control logic circuit situated to receive an output of the RBL, and a first multiplexer electrically coupled between the RBL and the timer and control logic circuit, the first multiplexer configured to set a replica word line (RWL) that controls, based on a state of select lines input into the first multiplexer and input provided by the timer and control logic, which of the RBCs is active.
Claims19
A memory control circuit comprising:
- a replica bit line (RBL) including a plurality of replica bit cells (RBCs) electrically coupled in series;
- a timer and control logic circuit situated to receive an output of the RBL;
- and
- a first multiplexer electrically coupled between the RBL and the timer and control logic circuit, the first multiplexer configured to set a replica word line (RWL) that controls, based on a state of select lines input into the first multiplexer and input provided by the timer and control logic, which of the RBCs is active.
A memory control circuit comprising:
- a first replica bit line (RBL) including a first plurality of replica bit cells (RBCs) electrically coupled in series;
- a second RBL including a second plurality of RBCs electrically coupled in series;
- and
- a timing and control logic circuit situated to receive an output of the first and second RBLs, wherein output of the first RBL is shorted to the output of the second RBL.
A memory circuit comprising:
- a memory comprising a plurality of bit cells (BCs);
- a replica bit line (RBL) including a plurality of replica bit cells (RBCs) electrically coupled in series;
- a sense amplifier configured to sense a differential voltage across one of the BCs;
- a timer and control logic circuit situated to receive an output of the RBL and control a state of the sense amplifier based on a state of the output of the RBL;
- and
- a first multiplexer electrically coupled between the RBL and the timer and control logic circuit, the first multiplexer configured to set a replica word line (RWL) that controls, based on a state of select lines input into the first multiplexer and input provided by the timer and control logic, which of the RBCs is active.
Dependencies are inferred from the claim text.