Apparatuses, systems, and methods for ODT pulse width duration determination

An apparatus comprising:

• a mode register configured to store an on-die termination (ODT) on latency and an ODT off latency;
• an ODT control circuit configured to compress the combined value of the ODT off latency and a cyclic redundancy check (CRC) bit based on the value of the ODT on latency and combine the compressed combined value of the ODT off latency and the CRC bit with the ODT on latency to generate an ODT offset value,
• wherein the ODT control circuit is further configured to receive a command signal and activate an ODT pulse signal in synchronization with an even divided clock or an odd divided clock based on when the command signal was received, and
• wherein the ODT pulse signal is active for a duration based, in part, on the ODT offset value;
• and
• a termination circuit configured to change a value of a termination resistor while the ODT pulse signal is active.

A method comprising:

• combining a cyclic redundancy check (CRC) bit with one of an ODT off latency and an ODT on latency to generate a first combined value;
• compressing the first combined value based off of the other of the ODT off latency and the ODT on latency;
• combining the compressed first combined value with the other of the ODT off latency and the ODT on latency to generate a second combined value;
• combining the second combined value with a burst length along an even path or an odd path to generate a third combined value;
• and
• activating an ODT pulse signal for a period of time based, at least in part, on the third combined value.