Method for adjusting logic states of data strobe signals used by memory device
AssigneeNanya Technology Corporation
InventorWu-Der Yang
Life of this patent
Estimating the term…
Abstract
A control unit in a memory and a method of controlling a memory are provided. The control unit includes a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage is configured to receive a first signal and a second signal. The second input stage is configured to receive the first signal and the second signal. The first output stage is connected to the first input stage and configured to generate a first processed signal. The second output stage is connected to the second input stage and configured to generate a second processed signal. If the first signal and the second signal are identical, the first processed signal and the second processed signal are different.
Claims13
A control unit of a memory, comprising:
- a first input stage configured to receive a first signal and a second signal;
- a second input stage configured to receive the first signal and the second signal;
- a first output stage connected to the first input stage and configured to generate a first processed signal;
- and
- a second output stage connected to the second input stage and configured to generate a second processed signal,
- wherein, if the first signal and the second signal are identical, the first processed signal and the second processed signal are different;
- wherein the first signal and the second signal are write data strobe signals;
- wherein the first output stage includes a first transistor and a first resistor connected to the first transistor and a ground, wherein the first transistor has a drain connected to the first input stage and a gate configured to receive the first signal, and a source configured to output the first processed signal.
A control unit of a memory, comprising:
- a first input stage configured to receive a first signal and a second signal;
- a second input stage configured to receive the first signal and the second signal;
- a first output stage connected to the first input stage and configured to generate a first processed signal;
- and
- a second output stage connected to the second input stage and configured to generate a second processed signal,
- wherein, if the first signal and the second signal are identical, the first processed signal and the second processed signal are different;
- wherein the first signal and the second signal are write data strobe signals;
- wherein the first input stage includes a first p-type transistor, a second p-type transistor, a first n-type transistor, and a second n-type transistor, and wherein the first p-type transistor and the first n-type transistor are connected in series and the second p-type transistor and the second n-type transistor are connected in series.
Dependencies are inferred from the claim text.