Concurrent scan operation on multiple blocks in a memory device

A method, comprising:

• selecting two or more blocks of a plurality of blocks in a memory array to concurrently scan during a scan operation to determine a reliability of data stored in the two or more blocks, the memory array comprising the plurality of blocks coupled to a set of sense amplifiers and a page buffer, each block of the plurality of blocks comprising a plurality of wordlines, wherein the memory array comprises a plurality of strings of memory cells spanning the plurality of blocks, and wherein each string of memory cells is associated with a respective sense amplifier and a respective logical segment of the page buffer, wherein respective dummy wordlines in the two or more blocks comprise transistors programmed in a staggered pattern, wherein one transistor in each block is programmed to a first threshold voltage and one or more remaining transistors in each block are programmed to a second threshold voltage that is higher than the first threshold voltage, and wherein the transistor programmed to the first threshold voltage is associated with a different logical segment of a page buffer and a different dummy wordline in each block;
• causing a first voltage to be applied to the respective dummy wordlines in the two or more blocks to selectively couple a string of memory cells in each block of the two or more blocks to a different sense amplifier of the set of sense amplifiers to enable concurrent reliability scanning of the two or more blocks;
• causing a second voltage to be applied to a selected word line of each block of the two or more blocks to read a bit stored at a respective memory cell of the string of memory cells in each block out to the set of sense amplifiers, wherein the bits from respective memory cells in each of the two or more blocks are read concurrently;
• and
• determining a scan result based on the concurrently read bits, wherein determining the scan result comprises determining one or more errors associated with storing data at the two or more blocks and calibrating the two or more blocks based on determining the one or more errors.

A memory device comprising:

• a memory array comprising a plurality of blocks coupled to a set of sense amplifiers and a page buffer, wherein each block comprises a respective dummy word line coupled with a plurality of strings of memory cells, and wherein each string of memory cells of the plurality of strings of memory cells comprises a transistor coupled with a respective sense amplifier of the set of sense amplifiers and is associated with a respective logical segment of the page buffer;
• and
• control logic, operatively coupled with the memory array, to perform operations comprising:
• selecting two or more blocks of the plurality of blocks to concurrently scan during a scan operation to determine a reliability of data stored in the two or more blocks, wherein the respective dummy word lines in the two or more blocks comprise transistors programmed in a staggered pattern, wherein one transistor associated with the dummy wordline in each block is programmed to a first threshold voltage and one or more remaining transistors associated with the dummy wordline in each block are programmed to a second threshold voltage that is higher than the first threshold voltage, and wherein the transistor programmed to the first threshold voltage is in a different string of memory cells and is associated with a different logical segment of the page buffer in each block;
• causing a first voltage to be applied to the respective dummy word line of each block to selectively activate a transistor of a string of memory cells in each block of the two or more blocks and couple respective strings of memory cells to respective sense amplifier of the set of sense amplifiers, the strings of memory cells in each block coupled to a different respective sense amplifier of the set of amplifiers to enable concurrent reliability scanning of the two or more blocks;
• causing a second voltage to be applied to a selected word line coupled to the plurality of strings of memory cells in each block of the two or more blocks to read a bit stored at a respective memory cell of a respective string of memory cells in each block out to the respective sense amplifiers of set of sense amplifiers, wherein the bits from respective memory cells in each of the two or more blocks are read concurrently;
• and
• determining a scan result based on the concurrently read bits, wherein determining the scan result comprises determining one or more errors associated with storing data at the two or more blocks and calibrating the two or more blocks based on determining the one or more errors.