Semiconductor storage device

A semiconductor storage device comprising:

• a memory cell array comprising first and second sub arrays respectively including a plurality of memory cells and simultaneously driven in a read operation or a write operation;
• a plurality of first lines each connected to the plurality of memory cells corresponding to one of a plurality of physical rows, where the physical row corresponds to the memory cells arranged in a first direction in the memory cell array;
• a plurality of second lines each connected to the plurality of memory cells arranged in a second direction intersecting with the first direction in the memory cell array;
• a decoder configured to select a selection line from among the first lines in accordance with a logical row address corresponding to each of the physical rows and to apply a read voltage or a write voltage to the selection line;
• and
• a sense amplifier configured to detect data from the second lines, wherein
• logical row addresses corresponding to physical rows adjacent to a certain physical row among the plurality of physical rows are fixed to differ between the first sub array and the second sub array, such that error bits are dispersed in terms of the logical row addresses for each of the first and second sub arrays.