Staggered write control for dual-interlocked cells
AssigneeMicron Technology, Inc.
InventorsHiroshi Akamatsu, Alex Joseph Kozlosky
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AssigneeMicron Technology, Inc.
InventorsHiroshi Akamatsu, Alex Joseph Kozlosky
Estimating the term…
Systems and methods include a memory device that includes a dual-interlocked cell (DICE) latch and upstream circuitry coupled to the DICE latch and including a common node configured to receive a control signal for an operation for the DICE latch. The upstream circuitry also includes a first divided control path coupled to common node and configured to generate a first divided control signal from the control signal. The upstream circuitry comprises a second divided control path coupled to the common node and configured to generate a second divided control signal from the control signal. The second divided control path includes a delay configured to delay the second divided control signal to stagger propagation of a potential neutron strike at the common node or upstream of the common node from the DICE latch.
A memory device, comprising:
A method for operating a memory device comprising:
A memory device, comprising:
Dependencies are inferred from the claim text.