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US 12,614,580 B2Granted
Semiconductor devices including a clock divider related to the generation of a command
AssigneeSK hynix Inc.
InventorsJung Taek You, Han Byeol Kwon, Kyu Young Kim
Life of this patent
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Abstract
A semiconductor device includes a clock division circuit configured to generate division clocks from a clock signal, based on a division enable signal that is activated based on a chip selection signal, and a valid time determination circuit configured to generate a valid signal for setting a generation time of a command, based on the chip selection signal and the division clocks.
Claims16
A semiconductor device comprising:
- a clock division circuit configured to receive a division enable signal to generate division clocks from a clock signal, when the division enable signal is activated based on a chip selection signal;
- and
- a valid time determination circuit configured to be electrically connected to the clock division circuit to generate a valid signal for setting a generation time of a command, based on the chip selection signal and the division clocks,
- wherein the valid time determination circuit is configured to detect a logic level of the chip selection signal in synchronization with one of the division clocks to generate the valid signal, and
- wherein the valid time determination circuit is configured to generate the valid signal that is activated at a valid command generation time when a detection condition of receiving the chip selection signal set to have a preset logic level in synchronization, at least two times, with one of the division clocks is satisfied.
2 more elements
A semiconductor device comprising:
- a division enable signal generation circuit configured to generate a division enable signal that is activated when a chip selection signal set to have a preset logic level is received in synchronization with a clock signal after exiting from a power-down section;
- and
- a valid time determination circuit configured to be electrically connected to the clock division circuit to generate a valid signal for setting a generation time of a command, based on division clocks generated based on the division enable signal and the chip selection signal,
- wherein the valid time determination circuit is configured to generate the valid signal that is activated at a valid command generation time when a detection condition of receiving the chip selection signal set to have a preset logic level in synchronization, at least two times, with one of the division clocks is satisfied.
1 more element
A semiconductor device comprising:
- a clock division circuit configured to receive a division enable signal to generate division clocks from a clock signal, when the division enable signal is activated based on a chip selection signal;
- and
- a valid time determination circuit configured to be electrically connected to the clock division circuit to generate a first valid signal and a second valid signal for setting a generation time of a command, based on the chip selection signal and the division clocks,
- wherein the valid time determination circuit is configured to generate the first valid signal that is activated at a first valid command generation time and generate the second valid signal that is activated at a second valid command generation time when a detection condition of receiving the chip selection signal set to have a preset logic level in synchronization with one of the division clocks is satisfied,
- wherein the valid time determination circuit is configured to generate the second valid signal that is activated at the second valid command generation time set as a time after the first valid command generation time.
2 more elements
Dependencies are inferred from the claim text.