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US 12,614,578 B2Granted
Memory device, a memory module, a computing system, a method for erasing a memory portion of a memory device and a method for generating an erase request
AssigneeIntel Corporation
InventorsShuo Liu, Yao Zu Dong, Qing Huang, Kevin Yufu Li, Yipeng Yao, Jie Yu
Life of this patent
Estimating the term…
Abstract
A memory device comprises an input interface configured to receive an erase request indicating a memory portion to be erased and control circuitry configured to trigger erasing information stored by memory cells of at least a part of the indicated memory portion of the memory device by writing a predefined pattern into the memory cells during an automatic refresh cycle.
Claims20
A memory device comprising:
- an input interface configured to receive an erase request indicating a memory portion to be erased;
- and
- control circuitry configured to trigger erasing information stored by memory cells of at least a part of the indicated memory portion of the memory device by writing a predefined pattern into the memory cells during an automatic refresh cycle.
A memory device comprising:
- an input interface configured to receive an erase request indicating at least a part of one row of memory cells to be erased, wherein the input interface is further configured to receive a read or write request for at least a part of a row of memory cells;
- and
- control circuitry configured to trigger a reset of at least a part of a row buffer of a memory array comprising the row of memory cells indicated by the read or write request based on a predefined pattern during a read or write cycle assigned for the received read or write request and before outputting of information stored by one or more memory cells indicated by the read or write request or before inputting information to be stored by one or more memory cells indicated by the read or write request, if an erase request was received for at least a part of the row of memory cells indicated by the read or write request.
A computing system comprising:
- one or more CPUs configured to run an operating system generating an operating system erase request indicating a high level memory address to be erased;
- and
- one or more memory controllers configured to determine a memory block of a DIMM based on the operating system erase request and generate a memory controller erase request indicating the memory block to be erased during an automatic refresh cycle or read/write cycle of the DIMM.
Dependencies are inferred from the claim text.