Half static random access memory (SRAM) cell
AssigneeSynopsys, Inc.
InventorRouwaida Kanj
Life of this patent
Estimating the term…
Abstract
An example is a method. A first logical value is written to a latch node of a latch circuit of a half static random access memory (SRAM) cell. A second logical value is read from the latch node. The latch circuit is non-inverter-based. The latch circuit includes a p-type transistor and an n-type transistor. A drain node of the p-type transistor is electrically connected to a gate node of the n-type transistor, and a drain node of the n-type transistor is electrically connected to a gate node of the p-type transistor. According to some examples, the half SRAM cell may be implemented as a storage node, for a physical unclonable function (PUF), and/or for data padding.
Claims20
A method comprising:
- writing a first logical value to a latch node of a latch circuit of a half static random access memory (SRAM) cell, the latch circuit being non-inverter-based, the latch circuit including:
- a p-type transistor;
- and
- an n-type transistor, wherein:
- a drain node of the p-type transistor is electrically connected to a gate node of the n-type transistor as a first node;
- and
- a drain node of the n-type transistor is electrically connected to a gate node of the p-type transistor as a second node, the latch circuit being configured to maintain the first node and the second node at logically complementary voltages;
- and
- reading a second logical value from the latch node.
A non-transitory storage medium storing an electronic representation of a circuit design, the circuit design comprising:
- a half static random access memory (SRAM) cell including a latch circuit, the latch circuit being non-inverter-based, the latch circuit including:
- a p-type transistor;
- and
- an n-type transistor, wherein:
- a drain node of the p-type transistor is electrically connected to a gate node of the n-type transistor as a first node;
- and
- a drain node of the n-type transistor is electrically connected to a gate node of the p-type transistor as a second node, the latch circuit being configured to maintain the first node and the second node at logically complementary voltages.
A method comprising:
- writing a first logical value to a latch node of a latch circuit of a half static random access memory (SRAM) cell, the latch circuit being non-inverter-based, the latch circuit consists of:
- a p-type transistor;
- and
- an n-type transistor, wherein:
- a source node of the p-type transistor is electrically connected to a first power supply node;
- a drain node of the p-type transistor is electrically connected to a gate node of the n-type transistor;
- a drain node of the n-type transistor is electrically connected to a gate node of the p-type transistor;
- and
- a source node of the n-type transistor is electrically connected to a second power supply node;
- and
- reading a second logical value from the latch node.
Dependencies are inferred from the claim text.