US 12,614,573 B2 · Impedance calibration circuit, semiconductor memory apparatus and memory system including impedance calibration circuit

Abstract

An impedance calibration circuit includes a code generation circuit and a code update control circuit. The code generation circuit generates a first impedance code set by performing an impedance adjustment operation within an activated period of a data output enable signal generated in response to a read command. The code update control circuit prevents updating a second impedance code set to the first impedance code set until deactivation of the data output enable signal, wherein the second impedance code set is used in impedance adjustment of a transmitting circuit.

Claims29

Dependent claims

An impedance calibration circuit comprising:

a code generation circuit configured to generate a first impedance code set by performing an impedance adjustment operation within an activated period of a data output enable signal generated in response to a read command;
and
a code update control circuit configured to prevent updating a second impedance code set to the first impedance code set until deactivation of the data output enable signal, wherein the second impedance code set is used in impedance adjustment of a transmitting circuit.

A semiconductor memory apparatus comprising:

a memory region;
a transmitting circuit configured to adjust an impedance according to a second impedance code set and configured to output data from the memory region during an activated period of a data output enable signal;
an impedance calibration circuit configured to perform an impedance adjustment operation within the activated period of the data output enable signal to generate a first impedance code set and configured to prevent updating the second impedance code set to the first impedance code set until deactivation of the data output enable signal;
and
a control circuit configured to activate the data output enable signal in response to a read command.

2 more elements

A memory system comprising:

a semiconductor memory apparatus comprising a transmitting circuit configured to adjust an impedance according to a second impedance code set, configured to perform an impedance adjustment operation within a data output period of the transmitting circuit in response to a read command to generate a first impedance code set, and configured to prevent a code update operation from updating the second impedance code set to the first impedance code set until the data output period is completed;
and
a controller configured to provide the semiconductor memory apparatus with an impedance control mode setting command to change timing of the code update operation.

Dependencies are inferred from the claim text.

Facts

Application

18/744,987Filed 17 Jun 2024

Priority

KR 10-2023-01766087 Dec 2023

Published

US 2025/0191623 A112 Jun 2025

Granted

28 Apr 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11C 7/1057
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output…
G11C 7/1084
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: data input buffers,…
G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
G11C 29/022
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in I/O circuitry

Impedance calibration circuit, semiconductor memory apparatus and memory system including impedance calibration circuit

Life of this patent

Impedance calibration circuit, semiconductor memory apparatus and memory system including impedance calibration circuit

Life of this patent

Abstract

Claims29