Shift register unit, gate driving circuit, and gate driving method

A shift register unit, comprising:

• a sensing control circuit connected to a first sensing control node, a sensing signal input terminal, a random signal input terminal, and a sensing active level supply terminal, and configured to write an active level signal provided by the sensing active level supply terminal to the first sensing control node in response to control of an active level signal provided by the random signal input terminal and an active level signal provided by the sensing signal input terminal;
• a first sensing input circuit connected to the first sensing control node, a clock control signal input terminal, and a first pull-up node, and configured to write an active level signal to the first pull-up node in response to control of an active level signal at the first sensing control node and an active level signal provided by the clock control signal input terminal;
• and
• a first driving output circuit connected to the first pull-up node, a first driving clock signal input terminal, and a first driving signal output terminal, and configured to write a signal provided by the first driving clock signal input terminal to the first driving signal output terminal in response to control of an active level signal at the first pull-up node,
• wherein the shift register unit further comprises:
• a first voltage control circuit connected to a first power supply terminal, the first pull-up node, and a first voltage control node, and configured to write an active level signal provided by the first power supply terminal to the first voltage control node in response to control of an active level signal at the first pull-up node;
• the shift register unit further comprises:
• a first sensing input anti-leakage circuit;
• and
• the first sensing input circuit is connected to the first pull-up node through the first sensing input anti-leakage circuit, and is connected to the first sensing input anti-leakage circuit at a first sensing input anti-leakage node, the first sensing input anti-leakage node is connected to the first voltage control node, the first sensing input anti-leakage circuit is connected to the clock control signal input terminal, and the first sensing input anti-leakage circuit is configured to form a path between the first sensing input anti-leakage node and the first pull-up node in response to control of an active level signal at the clock control signal input terminal, and cut off the path between the first sensing input anti-leakage node and the first pull-up node in response to control of an inactive level signal at the clock control signal input terminal,
• wherein the shift register unit further comprises:
• a second sensing input circuit connected to a second sensing control node, the clock control signal input terminal, and a second pull-up node, and configured to write an active level signal to the second pull-up node in response to control of an active level signal at the second sensing control node and an active level signal provided by the clock control signal input terminal, the second sensing control node being connected to the first sensing control node;
• and
• a third driving output circuit connected to the second pull-up node, a third driving clock signal input terminal, and a third driving signal output terminal, and configured to write a signal provided by the third driving clock signal input terminal to the third driving signal output terminal in response to control of an active level signal at the second pull-up node,
• wherein the second sensing input circuit comprises:
• an eighty-first transistor and an eighty-second transistor;
• a control electrode of the eighty-first transistor is connected to the clock control signal input terminal, a first electrode of the eighty-first transistor is connected to a second electrode of the eighty-second transistor, and a second electrode of the eighty-first transistor is connected to the second pull-up node;
• and
• a control electrode of the eighty-second transistor is connected to the second sensing control node, and a first electrode of the eighty-second transistor is connected to an input active level supply terminal.