GPU processor system

A GPU processor system, comprising:

• a set of N GPU chips {C1, C2, . . . , Cj, . . . , CN};
• a graphics memory H1j, which is irremovably coupled to a graphics card on which Cj is mounted;
• and
• a set of M separate graphics memory expansions {E1, E2, . . . , Ei, . . . , EM}, wherein:
• Cj includes:
• an unalterable graphics memory controller MC1j;
• and
• a set of N1(j) cross-chip interconnectors {FACj1, FACj2, . . . , FACjq(j)), . . . , FACjN1(j)};
• MC1j is configured to control access to H1j;
• Ei includes:
• a graphics memory controller MC2i;
• a graphics memory H2i;
• and
• a cross-chip interconnector SACi;
• MC2i is configured to control access to H2j;
• FACjq(j) and SACi are interconnected by a non-QPI interconnection bus;
• MC1j is unable to control access to H2i;
• MC2i is unable to control access to H1j;
• for any processor other than Cj:
• the processor has no access to MC2i;
• or
• the processor is given access to MC2i exclusively through FACjq(j) and SACi if the processor has access to MC2i;
• N is a positive integer;
• M is a positive integer;
• N1(j) is a positive integer;
• j is an integer ranging from 1 to N;
• Cj is the j-th GPU chip in the set of GPU chips;
• q(j) is an integer ranging from 1 to N1(j);
• FACjq(j) is the q(j)-th cross-chip interconnector on Cj;
• and
• i is an integer ranging from 1 to M.