Methods and apparatus to implement dual-attention vision transformers for interactive image segmentation

At least one non-transitory computer readable medium comprising instructions to cause at least one programmable circuit to at least:

• create a dual-attention tensor representation of an input tensor, the input tensor based on image data of an image, the dual-attention tensor representation to include an inter-attention tensor representation and an intra-attention tensor representation, the inter-attention tensor representation to describe a first correlation between a plurality of tensor crops partitioned from the input tensor, the intra-attention tensor representation to describe a second correlation between a plurality of layers in a tensor crop of the plurality of tensor crops;
• segment the image based on the dual-attention tensor representation to generate a segmentation mask, the segmentation mask to identify pixels of the image associated with an object in the image;
• and
• output the segmentation mask.

An apparatus for implementing interactive image segmentation, comprising:

• an image database;
• and
• processor circuitry including one or more of:
• at least one of a central processor unit, a graphic processor unit or a digital signal processor, the at least one of the central processor unit, the graphic processor unit or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations, the instructions in the apparatus;
• a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations;
• or
• an Application Specific Integrate Circuitry (ASIC) including logic gate circuitry to perform one or more third operations;
• the processor circuitry to perform at least one of the one or more first operations, the one or more second operations or the one or more third operations to instantiate:
• tensor crop partition circuitry to partition an input tensor into a plurality of tensor crops, the input tensor representing image data of an image;
• dual-attention calculation circuitry to create a dual-attention tensor representation of the input tensor, the dual-attention tensor representation to include an inter-attention tensor representation and an intra-attention tensor representation, the inter-attention tensor representation to describe a first correlation between the plurality of tensor crops, the intra-attention tensor representation to describe a second correlation between a plurality of layers in a tensor crop of the plurality of tensor crops;
• and
• decoder circuitry to:
• segment the image based on the dual-attention tensor representation to generate a segmentation mask, the segmentation mask to identify pixels of the image associated with an object in the image;
• and
• output the segmentation mask.