System and method for transistor placement in standard cell layout

A first memory of a non-transitory computer-readable media comprising computer-readable instructions which when executed by a processor cause the processor to:

• identify, within a transistor-level circuit representation stored in a second computer-readable memory, a plurality of output transistors in a circuit, wherein each of the plurality of output transistors comprises a drain terminal connected to an output of the circuit;
• select one or more pairs of transistors from the plurality of output transistors based upon a merging priority, wherein each pair of the one or more pairs comprises a first transistor and a second transistor that is of a same type as the first transistor;
• for each of the one or more pairs, combine an active region of the first transistor and the second transistor to form a mega transistor having a common active region that, in a corresponding physical layout, comprises a single contiguous diffusion region containing both a first drain terminal of the first transistor and a second drain terminal of the second transistor to provide a direct current path between the first drain terminal and the second drain terminal and to reduce parasitic resistance and capacitance relative to unmerged active regions;
• create, by a standard cell layout application, a standard cell layout of the circuit with the mega transistor, wherein creating the standard cell layout comprises replacing the first transistor and the second transistor of each of the one or more pairs with the mega transistor in the standard cell layout and generating geometric data defining the single contiguous diffusion region having a width and length according to predetermined design rules to maintain said reduced parasitic resistance and capacitance;
• generate, based on the standard cell layout and the geometric data, a representative data file configured to interface with fabrication tools to prepare a set of masks to fabricate the circuit;
• form an image on a first substrate to fabricate, using the representative data file, the set of masks, wherein the set of masks includes, on an active-region mask layer, a single active-area feature corresponding to the common active region to simultaneously pattern both the first drain terminal and the second drain terminal as portions of the same contiguous diffusion region;
• and
• fabricate, using the set of masks, a semiconductor device comprising the circuit including the mega transistor having the common active region, wherein the fabrication comprises forming the common active region over a second substrate.