Slack budgeting and discretization for a programmable device

A system comprising:

• a memory storing instructions;
• and
• a processor coupled with the memory, the processor configured to execute the instructions to cause the processor to:
• receive a physical circuit design file that includes physical circuit partitions that are each mapped to at least one of a first chip, a second chip, and a third chip,
• wherein the first chip and the second chip are connected by a first timing path, the second chip and the third chip are connected by a second timing path, wherein the first timing path and the second timing path each have an original path delay;
• determine a proportioned slack budget for each of the first timing path and the second timing path;
• determine, for each of the first timing path and the second timing path, a delay upper bound based on the original path delay and the slack budget of each timing path;
• update the delay upper bound of each timing path based on a shortest timing path delay;
• assign a multiplexing data ratio (XDR) value to the proportioned slack budget for each of the first timing path and the second timing path;
• adjust the XDR value based on reuse of existing wires in at least one of the first timing path and second timing path;
• determine an updated proportioned slack budget for each of the first timing path and the second timing path, based at least in part on the adjusted XDR value and the desired delay for each of the first timing path and second timing path;
• and
• adjust a routing of electronic signals along the first timing path and the second timing path, based on the proportioned slack budget.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to perform a method, comprising:

• receiving a physical circuit design file that includes physical circuit partitions that are each mapped to at least one of a first chip, second chip, and a third chip, wherein the first chip and the second chip are connected by a first timing path, the second chip and the third chip are connected by a second timing path, wherein the first timing path and the second timing path each have a desired delay;
• determining a total slack budget based on a driver clock period and a sum of the desired delay for the first timing path and the desired delay for the second timing path;
• proportioning the total slack budget to the first timing path and the second timing path based on the desired delay for each of the first timing path and the second timing path;
• and
• adjusting a routing of electronic signals along the first timing path and the second timing path, based on the proportional slack budget, including determining, for each of the first timing path and the second timing path, a delay upper bound and selecting a corresponding data-multiplexing value that satisfies the delay upper bound.