Distributed system on a chip memory access control

An apparatus comprising:

• a memory access control unit to control access of a device to a memory, wherein the memory access control unit is to access a memory access bridge table associated with an endpoint to which the device is coupled, the memory access bridge table having a first set of access information entries associated with a first isolated memory region of the memory and a second set of access information entries associated with a second isolated memory region of the memory, wherein the second set of access information entries contains less information than the first set of access information entries, wherein the first set of access information entries comprises memory address range information and device access information associated with the first isolated memory region of the memory and the second set of access information entries comprises memory address range information associated with the second isolated memory region and does not include device access information associated with the second isolated memory region, and wherein a transaction from the device directed to the first isolated memory region is authorized when the first set of access information entries indicates that the device is authorized, and wherein all transactions from the device directed to the second isolated memory are rejected;
• and
• circuitry to receive a memory transaction request from a device and to control access to the first isolated memory region and the second isolated memory region according to the first and second sets of access information entries in the memory access bridge table.

A method comprising:

• receiving a memory transaction request from a device;
• determining if the memory transaction request is directed to an isolated memory region of a memory and if the device has permission to access the isolated memory region, the determining including accessing a memory access table associated with an endpoint to which the device is coupled, the memory access table comprising:
• a first set of access information entries associated with a first isolated memory region of the memory and a second set of access information entries associated with a second isolated memory region of the memory,
• wherein the second set of access information entries contains less information than the first set of access information entries, wherein the first set of access information entries comprises memory address range information and device access information associated with the first isolated memory region of the memory and the second set of access information entries comprises memory address range information associated with the second isolated memory region and does not include device access information associated with the second isolated memory region, and wherein a transaction from the device directed to the first isolated memory region is authorized when the first set of access information entries indicates that the device is authorized, and wherein all transactions from the device directed to the second isolated memory are rejected;
• and
• rejecting the memory transaction request if the device is not authorized to access the isolated memory region.