Security isolation apparatus and method
AssigneeHuawei Technologies Co., Ltd.
InventorsJunhua Zhao, Tianhong Ding, Yanlei Jia, Qiang Xu
Life of this patent
Estimating the term…
Abstract
A system includes a first subsystem and a second subsystem that are used in a same chip. A security level of a first physical resource included in the first subsystem is higher than a security level of a second physical resource included in the second subsystem. The first subsystem includes an interrupt controller, and the interrupt controller is configured to manage an interrupt of a peripheral of the second subsystem. Embodiments of this application are for isolation between subsystems of different security levels in a chip.
Claims20
A security isolation apparatus, comprising:
- a chip comprising:
- a second subsystem comprising a second processor core, a first peripheral, and a second physical resource, wherein the second physical resource has a second security level;
- and
- a first subsystem comprising:
- a first processor core;
- a first physical resource, wherein the first physical resource has a first security level, and wherein the first security level is higher than the second security level;
- and
- an interrupt controller configured to:
- receive an interrupt signal from the first peripheral of the second subsystem;
- and
- control, when receiving the interrupt signal, the first processor core or the second processor core to suspend a running program and to execute a program from the interrupt signal.
A method comprising,
- providing a first subsystem and a second subsystem of a security isolation apparatus, wherein the first subsystem and the second subsystem are comprised in a same chip, wherein the first subsystem comprises a first processor core, an interrupt controller and a first physical resource having a first security level, wherein the second subsystem comprises a second processor core, a first peripheral, and a second physical resource having a second security level, and wherein the first security level is higher than the second security level;
- receiving, by the interrupt controller, an interrupt signal from the first peripheral of the second subsystem;
- and
- controlling, by the interrupt controller when receiving the interrupt signal, the first processor core or the second processor core to suspend a running program and execute a program from the interrupt signal.
A chip comprising:
- a second subsystem comprising a second processor core, a first peripheral, and a second physical resource, wherein the second physical resource has a second security level;
- and
- a first subsystem comprising:
- a first processor core;
- a first physical resource, wherein the first physical resource has a first security level, and wherein the first security level is higher than the second security level;
- and
- an interrupt controller configured to:
- receive an interrupt signal from the first peripheral of the second subsystem;
- and
- control, when receiving an interrupt signal, the first processor core or the second processor core to suspend a running program and to execute a program from the interrupt signal.
Dependencies are inferred from the claim text.