Reinforcement learning device and operation method thereof

A reinforcement learning device comprising:

• a computation circuit configured to perform an operation between a weight matrix and an input activation vector and to apply an activation function on an output of the operation to generate an output activation vector,
• wherein the computation circuit quantizes the input activation vector when a quantization delay time has elapsed since beginning of a learning operation and does not quantize the input activation vector otherwise,
• wherein the computation circuit includes:
• a processing element array including a plurality of processing elements configured to perform the operation on the weight matrix and the input activation vector;
• and
• an activation signal generation circuit configured to apply an activation function on an operation result output from the plurality of processing elements to generate the output activation vector,
• wherein each of the plurality of processing elements includes:
• a first buffer configured to store an element of the weight matrix;
• a second buffer configured to store at least one element of the input activation vector;
• a third buffer configured to store a result of the operation;
• a first multiplier configured to multiply a data stored in the first buffer with a first data which is a part of a data stored in the second buffer;
• a second multiplier configured to multiply the data stored in the second buffer and a second data which is a part of the data stored in the second buffer and which corresponds to a lower bit data than the first data;
• a shifter configured to shift an output of the first multiplier;
• a first adder configured to add an output of the shifter and an output of the second multiplier;
• and
• a second adder configured to add an output of the first adder and an output of the third buffer, and
• wherein each of the plurality of processing elements further includes:
• a first selection circuit configured to provide the output of the shifter or the output of the first multiplier according to a selection signal to the first adder, the selection signal indicating whether the quantization delay time has elapsed since beginning of the learning operation;
• a second selection circuit configured to provide the output of the second multiplier or first data from the third buffer to the first adder according to the selection signal;
• a third selection circuit configured to provide the output of the first adder or second data from the third buffer to the second adder according to the selection signal;
• a fourth selection circuit configured to provide the output of the third buffer or the output of the second multiplier to the second adder according to the selection signal;
• and
• a fifth selection circuit configured to provide an output of the second adder or the output of the first adder to the third buffer at a location for the first data from the third buffer according to the selection signal,
• wherein the output of the second adder is provided to the third buffer at a location for the second data from the third buffer.