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US 12,613,830 B2Granted
Accelerator architecture on a programmable platform
AssigneeAltera Corporation
InventorsDavid Shippy, Martin Langhammer, Jeffrey Eastlack
Life of this patent
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Abstract
An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.
Claims26
An integrated circuit comprising:
- an accelerator comprising processing nodes arranged in a grid, wherein each of the processing nodes comprises a vector processor that supports a vector data format, wherein the vector processor in each of the processing nodes comprises processing elements and a command processor that performs fetch and dispatch of first instructions for the processing elements, wherein each of the processing elements in the vector processor in each of the processing nodes comprises a multiplier, and wherein each of the processing nodes further comprises local memory;
- memory blocks;
- a dedicated control subsystem to execute software instructions and to control the processing nodes;
- and
- a mesh network that interconnects the processing nodes and the memory blocks.
2 more elements
A method for operating an integrated circuit:
- receiving, by an accelerator in the integrated circuit that comprises processing nodes arranged in a grid, a first set of software instructions using a mesh network that interconnects the processing nodes;
- executing a second set of software instructions using a dedicated control subsystem that controls the processing nodes, wherein the dedicated control subsystem is in the integrated circuit, wherein each of the processing nodes comprises local memory, and wherein each of the processing nodes further comprises a vector processor that supports a vector data format;
- and
- coordinating execution of the first set of software instructions for processing elements using a control processor, wherein the vector processor in each of the processing nodes comprises the processing elements and the control processor, and wherein each of the processing elements in the vector processor in each of the processing nodes comprises a multiplier.
1 more element
An integrated circuit comprising:
- an accelerator comprising processing nodes arranged in a grid, wherein each of the processing nodes comprises a vector processor, wherein each of the processing nodes further comprises local memory, wherein each of the processing nodes further comprises a processing element and a control processor that coordinates execution on functional units, and wherein the control processor performs fetch and dispatch of first instructions for the processing element, and wherein the processing element in each of the processing nodes comprises a multiplier;
- a network-on-a-chip that accesses software instructions from a second memory;
- a dedicated control subsystem that executes the software instructions and that controls the processing nodes;
- and
- a mesh network that interconnects the processing nodes.
2 more elements
Dependencies are inferred from the claim text.