Streamlined CXL memory fabric with lightweight scalable provisioning

An apparatus, comprising:

• a first Endpoint (EP1);
• a second Endpoint (EP2);
• and
• a computer configured to:
• receive, from a first host via the EP1, a CXL.mem Master-to-Subordinate Request (M2S Req) comprising:
• a MemRd* opcode, a first Tag, and a first physical address (PA) from a Host Physical Address (HPA) space of the first host (referred to as M2S Req MemRd*), wherein CXL denotes Compute Express Link (CXL);
• translate the M2S Req MemRd* to a CXL.cache Device-to-Host Request (D2H Req) comprising:
• a RdCurr opcode, a first Command Queue ID (CQID), and a second PA from an HPA space of the second host (referred to as D2H Req RdCurr);
• send, to a second host via the EP2, the D2H Req RdCurr;
• receive, via the EP1, a CXL.mem M2S Request with Data (M2S RwD) comprising:
• MemWr* opcode, *Data*, a second Tag, and a third PA (referred to as M2S RwD MemWr*);
• translate the M2S RwD MemWr* to a CXL.cache D2H Request comprising:
• a WrCur or a MemWr opcode, a second CQID, and a fourth PA (referred to as D2H Req WrCur/MemWr);
• and
• send, via the EP2, the D2H Req WrCur/MemWr.

A system, comprising:

• a first host;
• a second host;
• and
• a Resource Provisioning Unit (RPU) configured to:
• receive, from the first host, a CXL.mem Master-to-Subordinate Request (M2S Req) comprising:
• a MemRd* opcode, a first Tag, and a first physical address (PA) from a Host Physical Address (HPA) space of the first host (referred to as M2S Req MemRd*);
• wherein CXL denotes Compute Express Link (CXL);
• translate the M2S Req MemRd* to a CXL.cache Device-to-Host Request (D2H Req) comprising:
• a RdCurr opcode, a first Command Queue ID (CQID), and a second PA from an HPA space of the second host (referred to as D2H Req RdCurr);
• send, to the second host, the D2H Req RdCurr;
• receive, from the first host, a CXL.mem M2S Request with Data (M2S RwD) comprising:
• MemWr* opcode, *Data*, a second Tag, and a third PA (referred to as M2S RwD MemWr*);
• translate the M2S RwD MemWr* to a CXL.cache D2H Request comprising:
• a WrCur or a MemWr opcode, a second CQID, and a fourth PA (referred to as D2H Req WrCur/MemWr);
• and
• send, to the second host, the D2H Req WrCur/MemWr.

An apparatus, comprising:

• a first switch port;
• a second switch port;
• and
• a computer configured to:
• receive, via the first switch port, a CXL.mem Master-to-Subordinate Request (M2S Req) comprising:
• a MemRd* opcode, a first Tag, and a first physical address (PA) from a Host Physical Address (HPA) space of the first host (referred to as M2S Req MemRd*), wherein CXL denotes Compute Express Link (CXL);
• translate the M2S Req MemRd* to a CXL.cache Device-to-Host Request (D2H Req) comprising:
• a RdCurr opcode, a first Command Queue ID (CQID), and a second PA from an HPA space of the second host (referred to as D2H Req RdCurr);
• send, via the second switch port, the D2H Req RdCurr;
• receive, via the first switch port, a CXL.mem M2S Request with Data (M2S RwD) comprising:
• MemWr* opcode, *Data*, a second Tag, and a third PA (referred to as M2S RwD MemWr*);
• translate the M2S RwD MemWr* to a CXL.cache D2H Request comprising:
• a WrCur or a MemWr opcode, a second CQID, and a fourth PA (referred to as D2H Req WrCur/MemWr);
• and
• send, via the second switch port, the D2H Req WrCur/MemWr.