Parallel RAS channels in CXL memory device

A method performed by a CXL target controller in a memory device, the method comprising:

• exchanging flow control frames with a CXL host controller over a PCI interface, each flow control frame comprising a plurality of memory access requests;
• and
• in response to receiving a given memory access request in a flow control frame received from the CXL host controller, determining, among plural parallel reliability, availability and serviceability (RAS) channel datapaths on the memory device, a given RAS channel datapath to be accessed, and, based on accessing the given RAS channel datapath, determining a virtual channel and transmitting a given response to the given memory access request over the PCI interface using the determined virtual channel,
• wherein the memory device comprises a plurality of backend interfaces with each configured to connect to a respective media device, and wherein each RAS channel datapath is connected to one or more of the plurality of backend interfaces.