Cache memory system employing a multiple-level hierarchy cache coherency architecture

A method of maintaining cache coherency in a multi-level hierarchy cache memory system, comprising:

• receiving in a proxy cache controller circuit on a first die and communicatively coupled to a plurality of central processing unit (CPU) cores, a memory access request comprising a memory address from a first CPU core of the plurality of CPU cores in response to the first CPU core not being able to service the memory access request in a first cache memory of a plurality of cache memories assigned to the first CPU core;
• determining if the memory access request is able to be serviced in any other cache memories of the plurality of cache memories assigned to each of the other CPU cores of the plurality of CPU cores;
• and
• in response to determining the memory access request is not able to be serviced in any of the other cache memories:
• communicating the memory access request to a global cache controller circuit on a second die;
• receiving a valid cache state corresponding to the memory address in response to the global cache controller circuit determining that the memory access request is able to be serviced from another off-die cache memory;
• and
• updating the valid cache state for the memory address associated with the memory access request.

A non-transitory computer-readable medium having stored thereon computer executable instructions which, when executed by a proxy cache controller circuit on a first die and communicatively coupled to a plurality of central processing unit (CPU) cores, cause the proxy cache controller circuit to:

• receive in a memory access request comprising a memory address from a first CPU core of the plurality of CPU cores in response to the first CPU core not being able to service the memory access request in a first cache memory of a plurality of cache memories assigned to the first CPU core;
• determine if the memory access request is able to be serviced in any other cache memories of the plurality of cache memories assigned to each of the other CPU cores of the plurality of CPU cores;
• and
• in response to determining the memory access request is not able to be serviced in any of the other cache memories:
• communicate the memory access request to a global cache controller circuit on a second die;
• receive a valid cache state corresponding to the memory address in response to the global cache controller circuit determining that the memory access request is able to be serviced from another off-die cache memory;
• and
• update the valid cache state for the memory address associated with the memory access request.

A processor-based system, comprising:

• a first die, comprising:
• a first processor comprising one or more first central processing unit (CPU) cores;
• a first local cache memory comprising one or more first cache memories each assigned to a first CPU core of the one or more first CPU cores;
• and
• a first proxy cache controller circuit communicatively coupled to the one or more first CPU cores;
• and
• a second die, comprising:
• a second processor comprising one or more second CPU cores;
• a second local cache memory comprising one or more second cache memories each assigned to a second CPU core of the one or more second CPU cores;
• and
• a second proxy cache controller circuit communicatively coupled to the one or more second CPU cores;
• and
• a cache memory system, comprising:
• a global cache controller circuit;
• the first proxy cache controller circuit;
• and
• the second proxy cache controller circuit;
• the first CPU core of the one or more first CPU cores configured to:
• issue a memory access request to a memory address in a first cache memory of the one or more first cache memories assigned to the first CPU core;
• communicate the memory access request to the first proxy cache controller circuit in response to the first CPU core not being able to service the memory access request in the first cache memory;
• the first proxy cache controller circuit in the first CPU core configured to:
• determine if the memory access request is able to be serviced in any first cache memory of the one or more first cache memories assigned to the other first CPU cores of the one or more first CPU cores;
• and
• in response to determining the memory access request is not able to be serviced in any of the other first cache memories:
• communicate the memory access request to the global cache controller circuit;
• the global cache controller circuit configured to:
• determine if the memory access request is able to be serviced in any second cache memory of the one or more second cache memories;
• in response to determining the memory access request is able to be serviced in a second cache memory of the one or more second cache memories:
• communicate the memory access request to the second proxy cache controller circuit to be serviced in the second cache memory;
• receive a valid cache state corresponding to the memory address in response to determining that the memory access request is able to be serviced in the second cache memory of the one or more second cache memories;
• and
• update the valid cache state for the memory address associated with the memory access request based on the serviced memory access request in the second local cache memory.