Method for memory ID allocation, memory, memory module, and memory system

A method for memory identification (ID) allocation, the method comprising:

• receiving from a management bus, by a first memory, a second memory, a third memory, and a fourth memory, information to set IDs to a first value;
• setting, by the first memory, an ID for the first memory to the first value after an activation signal is input to an ID input terminal of the first memory;
• outputting, by the first memory, the activation signal to an ID output terminal of the first memory,
• wherein the ID output terminal of the first memory is electrically connected to an ID input terminal of the second memory;
• receiving from the management bus, by the first memory, the second memory, the third memory, and the fourth memory, information to set the IDs to a second value;
• setting, by the second memory having an unset ID, an ID for the second memory to the second value after the activation signal is input to an ID input terminal of the second memory;
• and
• outputting, by the second memory, the activation signal to an ID output terminal of the second memory,
• wherein the ID output terminal of the second memory is electrically connected to an ID input terminal of the third memory.

A memory system comprising:

• a command address bus;
• a plurality of data buses;
• a management bus;
• a plurality of memories connected in series, commonly connected to the management bus, commonly connected to the command address bus, and connected to corresponding data buses among the plurality of data buses, and
• wherein each of the plurality of memories includes an identification (ID) input terminal and an ID output terminal;
• a memory controller connected to the plurality of memories through the command address bus and the plurality of data buses;
• and
• a baseboard management controller connected to the plurality of memories through the management bus;
• wherein an activation signal is input to an ID input terminal of a memory among the plurality of memories, and the memory sets an ID for the memory in response to ID setting information transmitted by the baseboard management controller on the management bus, and
• wherein for each of the plurality of memories, a memory does not decode the ID setting information after the ID of the memory is set.

A memory module comprising:

• a management bus;
• and
• a plurality of memories connected to the management bus;
• wherein an identification (ID) output terminal of a memory of the plurality of memories is connected to an ID input terminal of a following memory of the plurality of memories such that the plurality of memories are connected in series;
• wherein, when an activation signal is applied to an ID input terminal of the memory, the memory sets an ID for the memory in response to ID setting information transmitted on the management bus and provides an output signal to the ID output terminal such that the output signal affects setting an ID for the following memory, and
• wherein for each of the plurality of memories, a memory does not decode the ID setting information after the ID of the memory is set.