Semiconductor system

A semiconductor system comprising:

• a system chip comprising a first system interface, a second system interface, a third system interface, and a fourth system interface and configured to output, when a fail occurs in the fourth system interface, a first request, a second request, a third request, and a fourth request as a first transfer request, a second transfer request, a third transfer request, and a fourth transfer request through the first system interface, the second system interface, and the third system interface, wherein the first system interface and the second system interface are adjacent to the fourth system interface;
• an interposer comprising a plurality of wires and configured to output the first transfer request, the second transfer request, the third transfer request, and the fourth transfer request as a first input request, a second input request, a third input request, and a fourth input request through the plurality of wires;
• and
• a base chip comprising a first high bandwidth memory (HBM) interface, a second HBM interface, a third HBM interface, and a fourth HBM interface and configured to receive, when a fail occurs in the fourth HBM interface, the first input request, the second input request, the third input request, and the fourth input request from the first HBM interface, the second HBM interface, and the third HBM interface, wherein the first HBM interface and the second HBM interface are adjacent to the fourth HBM interface.

A semiconductor system comprising:

• a system chip comprising a first system interface, a second system interface, a third system interface, and a fourth system interface and configured to output a first request, a second request, a third request, and a fourth request as a first transfer request, a second transfer request, a third transfer request, and a fourth transfer request through the first system interface, the second system interface, the third system interface, and the fourth system interface, configured to split the first request, the second request, the third request, and the fourth request through a system interface in which a fail has not occurred by bypassing a system interface in which a fail occurred among the first system interface, the second system interface, the third system interface, and the fourth system interface, and configured to output a split first request, a split second request, a split third request, and a split fourth request as the first transfer request, the second transfer request, the third transfer request, and the fourth transfer request;
• an interposer comprising a plurality of wires and configured to output the first transfer request, the second transfer request, the third transfer request, and the fourth transfer request as a first input request, a second input request, a third input request, and a fourth input request through the plurality of wires;
• and
• a base chip comprising a first high bandwidth memory (HBM) interface, a second HBM interface, a third HBM interface, and a fourth HBM interface and configured to receive the first input request, the second input request, the third input request, and the fourth input request from the first HBM interface, the second HBM interface, the third HBM interface, and the fourth HBM interface, configured to receive the first input request, the second input request, the third input request, and the fourth input request from an HBM interface in which a fail has not occurred by bypassing an HBM interface in which a fail occurred among the first HBM interface, the second HBM interface, the third HBM interface, and the fourth HBM interface, and configured to transmit the first input request, the second input request, the third input request, and the fourth input request to a plurality of channels of a stack memory device by splitting the first input request, the second input request, the third input request, and the fourth input request.