Parity cache for raid reliability, accessibility, and serviceability of a memory device
AssigneeMicron Technology, Inc.
InventorsPatrick Estep, Stephen Pawlowski, Emanuele Confalonieri, Nicola Del Gatto, Paolo Amato
Life of this patent
Estimating the term…
Abstract
There are provided methods and systems for improving RAS features of a memory device. For example, there is provided a system that includes a memory and a memory side cache. The system further includes a processor that is configured to minimize accesses to the memory by executing certain operations. The operations can include computing a new parity based on old data, new data, and an old parity in response to data from the memory side cache being written to the memory.
Claims16
A system, comprising:
- a memory device;
- a memory side cache configured for storing frequently accessed data and corresponding parity data to increase data read and write operations to and from the memory device;
- a parity cache configured for storing a new parity data, wherein the parity cache is located between the memory side cache and the memory device such that the parity cache is deployed as a separate, last level cache on the memory device;
- and
- a processor configured to minimize access to the memory device by executing operations including:
- (i) for every data update to the memory side cache, the system determines whether or not a cacheline for the data update is already in the parity cache;
- (ii) when the cacheline for the data update is not already in the parity cache, the cacheline is brought into the parity cache, the system reads an old parity data, and computes the new parity data using old data, new data, and the old parity data;
- (i) writes the new parity data only into the parity cache, wherein the parity cache is a single channel dedicated for all storage and subsequent access to the new parity data;
- (iii) when the operations evict a dirty line from the memory side cache, the new parity data has already been calculated and written to the parity cache;
- and
- (iv) the parity cache and the memory side cache are configured to operate together to cause at least a 20% reduction in an amount of data transferred to and from the memory device with the parity cache that is sized approximately ⅛th as big as the memory side cache.
A method for use by a memory controller of a memory device, the method comprising:
- storing frequently accessed data and corresponding parity data into a memory side cache to increase data read and write operations to and from the memory device;
- storing new parity data into a parity cache, wherein the parity cache is located between the memory side cache and the memory device such that the parity cache is deployed as a separate, last level cache on a memory device;
- for every data update to the memory side cache, determining whether or not a cacheline for the parity update is already in the parity cache;
- when the cacheline for the data update is not already in the parity cache, the cacheline is brought into the parity cache, then reading an old parity data, and computing a new parity using old data, new data, and the old parity;
- writing the new parity data only into the parity cache, wherein the parity cache is a single channel dedicated for all storage and subsequent access to the new parity data;
- when evicting a dirty line from the memory side cache, the new parity data has already been calculated and written to the parity cache;
- and
- operating together the parity cache and the memory side cache to cause at least a 20% reduction in an amount of data transferred to and from the memory device with the parity cache that is sized approximately ⅛th as big as the memory side cache.
Dependencies are inferred from the claim text.